original_signal.tan.rpt

一种基于LUT的预失真方法。其中的一部分

+----------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------+------------------------+-------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------+
; Type                                                                                   ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                ; To                     ; From Clock                                                              ; To Clock                                                                ; Failed Paths ;
+----------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------+------------------------+-------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------+
; Worst-case tsu                                                                         ; N/A       ; None                             ; 6.731 ns                         ; RstN                                                                                                ; mod:inst4|rposition[9] ; --                                                                      ; clkin                                                                   ; 0            ;
; Worst-case tco                                                                         ; N/A       ; None                             ; 5.243 ns                         ; mod:inst4|rfout[18]                                                                                 ; dataout[15]            ; clkin                                                                   ; --                                                                      ; 0            ;
; Worst-case th                                                                          ; N/A       ; None                             ; -3.632 ns                        ; RstN                                                                                                ; FIRInterp:inst8|we     ; --                                                                      ; clkin                                                                   ; 0            ;
; Clock Setup: 'altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]' ; 6.260 ns  ; 65.56 MHz ( period = 15.254 ns ) ; 111.19 MHz ( period = 8.994 ns ) ; FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 ; FIRInterp:inst8|Md[9]  ; altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] ; altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] ; 0            ;
; Clock Hold: 'altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]'  ; -2.079 ns ; 65.56 MHz ( period = 15.254 ns ) ; N/A                              ; CLK_ALL_GEN:inst5|count[4]                                                                          ; FIRInterp:inst8|we     ; altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] ; altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] ; 21           ;
; Total number of failed paths                                                           ;           ;                                  ;                                  ;                                                                                                     ;                        ;                                                                         ;                                                                         ; 21           ;
+----------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------+------------------------+-------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                                                  ;
+-------------------------------------------------------+--------------------+------+-------------------------------------------------------------------------+-------------+
; Option                                                ; Setting            ; From ; To                                                                      ; Entity Name ;
+-------------------------------------------------------+--------------------+------+-------------------------------------------------------------------------+-------------+
; Device Name                                           ; EP3C25Q240C8       ;      ;                                                                         ;             ;
; Timing Models                                         ; Preliminary        ;      ;                                                                         ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;                                                                         ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;                                                                         ;             ;
; Cut off read during write signal paths                ; On                 ;      ;                                                                         ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;                                                                         ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;                                                                         ;             ;
; fmax Requirement                                      ; 140 MHz            ;      ;                                                                         ;             ;
; Ignore Clock Settings                                 ; On                 ;      ;                                                                         ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;                                                                         ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;                                                                         ;             ;
; Enable Clock Latency                                  ; Off                ;      ;                                                                         ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;                                                                         ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;                                                                         ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;                                                                         ;             ;
; Number of paths to report                             ; 200                ;      ;                                                                         ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;                                                                         ;             ;
; Use Fast Timing Models                                ; Off                ;      ;                                                                         ;             ;
; Report IO Paths Separately                            ; Off                ;      ;                                                                         ;             ;
; Clock Settings                                        ; clk_3M             ;      ; CLK_ALL_GEN:inst5|count[4]                                              ;             ;
; Clock Settings                                        ; clk_70M            ;      ; altpll0:inst6|altpll:altpll_component|altpll_7f31:auto_generated|clk[0] ;             ;
; Clock Settings                                        ; clk                ;      ; clkin                                                                   ;             ;
; Clock Settings                                        ; clk_70M            ;      ; pin_name                                                                ;             ;
+-------------------------------------------------------+--------------------+------+-------------------------------------------------------------------------+-------------+