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7'h37: data=26'h3c62a98;
7'h38: data=26'h3c40ac7;
7'h39: data=26'h3c1eaf7;
7'h3a: data=26'h3bfcb26;
7'h3b: data=26'h3bd8b55;
7'h3c: data=26'h3bb4b84;
7'h3d: data=26'h3b90bb3;
7'h3e: data=26'h3b6abe1;
7'h3f: data=26'h3b46c10;
7'h40: data=26'h3b1ec3f;
7'h41: data=26'h3af8c6d;
7'h42: data=26'h3ad0c9b;
7'h43: data=26'h3aaacc9;
7'h44: data=26'h3a80cf7;
7'h45: data=26'h3a58d25;
7'h46: data=26'h3a2ed53;
7'h47: data=26'h3a04d81;
7'h48: data=26'h39dadae;
7'h49: data=26'h39aeddb;
7'h4a: data=26'h3982e09;
7'h4b: data=26'h3956e36;
7'h4c: data=26'h3928e63;
7'h4d: data=26'h38fce90;
7'h4e: data=26'h38ceebc;
7'h4f: data=26'h389eee9;
7'h50: data=26'h3870f15;
7'h51: data=26'h3840f41;
7'h52: data=26'h3810f6e;
7'h53: data=26'h37e0f9a;
7'h54: data=26'h37aefc5;
7'h55: data=26'h377cff1;
7'h56: data=26'h374b01c;
7'h57: data=26'h3717048;
7'h58: data=26'h36e5073;
7'h59: data=26'h36b109e;
7'h5a: data=26'h367b0c9;
7'h5b: data=26'h36470f4;
7'h5c: data=26'h361111e;
7'h5d: data=26'h35db149;
7'h5e: data=26'h35a5173;
7'h5f: data=26'h356d19d;
7'h60: data=26'h35371c7;
7'h61: data=26'h34ff1f0;
7'h62: data=26'h34c521a;
7'h63: data=26'h348d243;
7'h64: data=26'h345326c;
7'h65: data=26'h3419295;
7'h66: data=26'h33dd2be;
7'h67: data=26'h33a32e7;
7'h68: data=26'h336730f;
7'h69: data=26'h332b338;
7'h6a: data=26'h32ef360;
7'h6b: data=26'h32b1388;
7'h6c: data=26'h32733af;
7'h6d: data=26'h32353d7;
7'h6e: data=26'h31f73fe;
7'h6f: data=26'h31b7425;
7'h70: data=26'h317944c;
7'h71: data=26'h3139473;
7'h72: data=26'h30f749a;
7'h73: data=26'h30b74c0;
7'h74: data=26'h30754e6;
7'h75: data=26'h303350c;
7'h76: data=26'h2ff1532;
7'h77: data=26'h2faf557;
7'h78: data=26'h2f6b57d;
7'h79: data=26'h2f275a2;
7'h7a: data=26'h2ee35c7;
7'h7b: data=26'h2e9f5ec;
7'h7c: data=26'h2e59610;
7'h7d: data=26'h2e15634;
7'h7e: data=26'h2dcf658;
7'h7f: data=26'h2d8767c;
default: data = 0;
endcase
always@(posedge SYSCLK )
begin
DATAW<=data;
end
endmodule
module mux(
RESET,//system reset.
CLK, //system clock.
CTL2, //mux1~4's control bit.
DATAW,
DATAC,
OCTL2,//output CTL2
W1, //output sin wave. mux1 output.
W2, //output cos wave. mux3 output.
C1, //output sin coefficient.mux2 output.
C2); //output cos coefficient.mux4 output.
//Wordlength of Wave value,k bits
parameter WAVE_BITS = 0;
//Wordlength of coefficients value,i bits
parameter COEFF_BITS =0;
input CLK,CTL2,RESET;
input[WAVE_BITS+WAVE_BITS-1:0] DATAW;
input[COEFF_BITS+COEFF_BITS-1:0] DATAC;
output[WAVE_BITS-1:0] W1,W2;
output[COEFF_BITS-1:0] C1,C2;
output OCTL2;
reg[WAVE_BITS+WAVE_BITS-1:0] dataw;
reg[COEFF_BITS+COEFF_BITS-1:0] datac;
reg[WAVE_BITS-1:0] W1,W2,W22,W11;
reg[COEFF_BITS-1:0] C11,C22,C1,C2;
wire[WAVE_BITS-1:0] WS,WC;
wire[COEFF_BITS-1:0] CA,CB;
assign WS[WAVE_BITS-1:0]=dataw[WAVE_BITS-1:0];
assign WC[WAVE_BITS-1:0]=dataw[WAVE_BITS+WAVE_BITS-1:WAVE_BITS];
assign CA[COEFF_BITS-1:0]=datac[COEFF_BITS-1:0];
assign CB[COEFF_BITS-1:0]=datac[COEFF_BITS+COEFF_BITS-1:COEFF_BITS];
assign OCTL2=CTL2;
always@(CTL2 or WS or WC or CA or CB)
case(CTL2)
1'b0: begin
W11<=WS;
W22<=WC;
C11<=CA;
C22<=CB;
end
1'b1: begin
W11<=WC;
W22<=WS;
C11<=CB;
C22<=CA;
end
endcase
always@(posedge CLK or posedge RESET)
begin
if(RESET)
begin
C1<=0;
C2<=0;
W1<=0;
W2<=0;
dataw<=0;
datac<=0;
end
else
begin
C1<=C11;
C2<=C22;
W1<=W11;
W2<=W22;
dataw<=DATAW;
datac<=DATAC;
end
end
endmodule
module muad(
RESET,
CLK, //system clock.
CTL2, //control add or sub
W1, //wave value input,from the mux1.
W2, //wave value input,from the mux3.
C1, //coefficient input,from the mux2.
C2, //coefficient input,from the mux4.
ADDRN, //interpolation address.
OUTS, //k bits output sin wave data,without signed bit.
OUTC); //k bits output cos wave data,without signed bit.
//Wordlength of Wave value,k bits
parameter WAVE_BITS =0;
//Wordlength of coefficients value,i bits
parameter COEFF_BITS =0;
//interpolation data wordlength j=ceil(log2(2pi(2^n-1)/2^(n+m+3)(2^k-1))).(6)
parameter INTER_BITS =0;
//interpolatin address bit
parameter ADDR_N =0;
input RESET,CLK,CTL2;
input[WAVE_BITS-1:0] W1,W2;
input[COEFF_BITS-1:0] C1,C2;
input[ADDR_N-1:0] ADDRN;
output[WAVE_BITS-1:0] OUTS,OUTC;
reg[INTER_BITS:0] inter1,inter2;
reg[WAVE_BITS-1:0] OUTS,OUTC,OUTST,OUTCT;
reg[INTER_BITS-1:0] inter1_,inter2_;
reg round1,round2,subround1,subround2;
wire OCTL,OCTL2;
wire[ADDR_N-1:0] OADDRN;
wire[WAVE_BITS-1:0] ow1,ow2,OUTS1,OUTC1,OUTS2,OUTC2;
wire[INTER_BITS:0] inter11,inter22;
always@(posedge CLK or posedge RESET)
begin
if(RESET)
begin
round1 <=0;
round2 <=0;
subround1 <=1;
subround2 <=1;
OUTS <=0;
OUTC <=0;
inter1_ <=0;
inter2_ <=0;
inter1 <=0;
inter2 <=0;
end
else
begin
inter1 <=inter11;// (ADDRN2*C1);
inter2 <=inter22;// ADDRN2*C2;
inter1_[INTER_BITS-1:0]<=inter1[INTER_BITS:1];
inter2_[INTER_BITS-1:0]<=inter2[INTER_BITS:1];
round1 <=inter1[0];
round2 <=inter2[0];
subround1 <=~inter1[0];
subround2 <=~inter2[0];
OUTS <=OUTST;
OUTC <=OUTCT;
end
end
always@(OCTL2 or OUTS1 or OUTS2 or OUTC1 or OUTC2)
case(OCTL2)
1'b0: begin
OUTST<=OUTS1; //w1_+inter1_1+round1
OUTCT<=OUTC1; //w2_-inter2_1-round2
end
1'b1: begin
OUTST<=OUTS2; //w1_-inter1_1-round1
OUTCT<=OUTC2; //w2_+inter2_1+round2
end
endcase
add U_add(
.dataa(ow1),
.datab(inter1_),
.cin(round1),
.clock(CLK),
.result(OUTS1));
sub U_sub(
.dataa(ow2),
.datab(inter2_),
.cin(subround2),
.clock(CLK),
.result(OUTC1));
sub U1_sub(
.dataa(ow1),
.datab(inter1_),
.cin(subround1),
.clock(CLK),
.result(OUTS2));
add U1_add(
.dataa(ow2),
.datab(inter2_),
.cin(round2),
.clock(CLK),
.result(OUTC2));
mult U_mult(
.dataa(OADDRN),
.datab(C1),
.clock(CLK),
.result(inter11));
mult U1_mult(
.dataa(OADDRN),
.datab(C2),
.clock(CLK),
.result(inter22));
delayl U_delayl(
.CLK(CLK),
.RESET(RESET),
.ADDRN(ADDRN),
.CTL2(CTL2),
.W1(W1),
.W2(W2),
.OADDRN(OADDRN),
.OCTL2(OCTL2),
.ow1(ow1),
.ow2(ow2));
defparam U_delayl.WAVE_BITS=WAVE_BITS;
defparam U_delayl.COEFF_BITS=COEFF_BITS;
defparam U_delayl.INTER_BITS=INTER_BITS;
defparam U_delayl.ADDR_N=ADDR_N;
endmodule
module delayl(
CLK,
RESET,
ADDRN,
CTL2,
W1,
W2,
OADDRN,
OCTL2,
ow1,
ow2);
//Wordlength of Wave value,k bits
parameter WAVE_BITS =0;
//Wordlength of coefficients value,i bits
parameter COEFF_BITS =0;
//interpolation data wordlength j=ceil(log2(2pi(2^n-1)/2^(n+m+3)(2^k-1))).(6)
parameter INTER_BITS =0;
//interpolatin address bit
parameter ADDR_N =0;
input RESET,CLK,CTL2;
input[WAVE_BITS-1:0] W1,W2;
input[ADDR_N-1:0] ADDRN;
output[WAVE_BITS-1:0] ow1,ow2;
output[ADDR_N-1:0] OADDRN;
output OCTL2;
reg CTL2_,CTL2_1,CTL2_2,CTL2_3,CTL2_4,OCTL2;//,CTL2_5;//,CTL2_6;
reg[ADDR_N-1:0] ADDRN1,ADDRN2,OADDRN;
reg[WAVE_BITS-1:0] w1,w2,w1_,w2_,w1_1,w2_1,w1_2,w2_2,ow1,ow2;
always@(posedge CLK or posedge RESET)
begin
if(RESET)
begin
ADDRN1<=0;
ADDRN2<=0;
OADDRN<=0;
CTL2_<=0;
CTL2_1<=0;
CTL2_2<=0;
CTL2_3<=0;
CTL2_4<=0;
OCTL2<=0;
w1<=0;
w2<=0;
w1_<=0;
w2_<=0;
w1_1<=0;
w2_1<=0;
//w1_2<=0;
//w2_2<=0;
ow1<=0;
ow2<=0;
end
else
begin
w1<=W1;
w2<=W2;
w1_<=w1;
w2_<=w2;
w1_1<=w1_;
w2_1<=w2_;
ow1<=w1_1;
ow2<=w2_1; //W1,W2 delayl 3 CLK;
CTL2_<=CTL2;
CTL2_1<=CTL2_;
CTL2_2<=CTL2_1;
CTL2_3<=CTL2_2;
CTL2_4<=CTL2_3;
OCTL2<=CTL2_4; //CTL2 delayl 4 CLK
ADDRN1<=ADDRN;
ADDRN2<=ADDRN1;
OADDRN<=ADDRN2; //ADDRN delayl 2 CLK
end
end
endmodule
//`include "addo.v"
module out(
RESET,
CLK, //system clk.
OCLK,
CTL3, //sin wave sign bit.
CTL4, //cos wave sign bit.
DATAS, //sin wave value.
DATAC, //cos wave value.
OUTS, //sinwave value with signed bit.
OUTC); //coswave value with signed bit.
//Wordlength of Wave value,k bits
parameter WAVE_BITS =13;
input RESET,CLK,CTL3,CTL4;
input[WAVE_BITS-1:0] DATAS,DATAC;
output OCLK;
output[WAVE_BITS:0] OUTS,OUTC;
reg[WAVE_BITS:0] OUTS_,OUTC_,OUTS_1,OUTC_1,OUTST_1,OUTCT_1,OUTS,OUTC,ADDOUTS_2,ADDOUTC_2,OUTS_2,OUTC_2;
reg CTL3_,CTL4_;
wire OCLK;
wire[1:0] sign;
wire[WAVE_BITS:0] ADDOUTS_1,ADDOUTC_1;
wire[WAVE_BITS-1:0] invert_datas,invert_datac;
assign OCLK=CLK;
assign sign[0]=CTL4_;
assign sign[1]=CTL3_;
assign invert_datas=~DATAS[WAVE_BITS-1:0];
assign invert_datac=~DATAC[WAVE_BITS-1:0];
always@(posedge CLK or posedge RESET)
begin
if(RESET)
begin
CTL3_<=0;
CTL4_<=0;
OUTS_1<=0;
OUTC_1<=0;
OUTC<=0;
OUTS<=0;
ADDOUTS_2<=0;
ADDOUTC_2<=0;
end
else
begin
CTL3_<=CTL3;
CTL4_<=CTL4;
//OUTS[WAVE_BITS]<=~OUTS_[WAVE_BITS]; //OUTS and OUTC are unsign date
//OUTS[WAVE_BITS-1:0]<=OUTS_[WAVE_BITS-1:0];
//OUTC[WAVE_BITS]<=~OUTC_[WAVE_BITS];
//OUTC[WAVE_BITS-1:0]<=OUTC_[WAVE_BITS-1:0];
OUTC<=OUTC_;
OUTS<=OUTS_;
OUTS_1<=OUTST_1;
OUTC_1<=OUTCT_1;
OUTS_2<=OUTS_1;
OUTC_2<=OUTC_1;
ADDOUTS_2<=ADDOUTS_1;
ADDOUTC_2<=ADDOUTC_1;
end
end
always@(sign or DATAS or DATAC or CTL3_ or CTL4_ or invert_datac or invert_datas)
begin
OUTST_1[WAVE_BITS]<=CTL3_;
OUTCT_1[WAVE_BITS]<=CTL4_;
case(sign)
2'b00:
begin
OUTST_1[WAVE_BITS-1:0]<=DATAS[WAVE_BITS-1:0];
OUTCT_1[WAVE_BITS-1:0]<=DATAC[WAVE_BITS-1:0];
end
2'b01:
begin
OUTST_1[WAVE_BITS-1:0]<=DATAS[WAVE_BITS-1:0];
OUTCT_1[WAVE_BITS-1:0]<=invert_datac[WAVE_BITS-1:0];
end
2'b11:
begin
OUTST_1[WAVE_BITS-1:0]<=invert_datas[WAVE_BITS-1:0];
OUTCT_1[WAVE_BITS-1:0]<=invert_datac[WAVE_BITS-1:0];
end
2'b10:
begin
OUTST_1[WAVE_BITS-1:0]<=invert_datas[WAVE_BITS-1:0];
OUTCT_1[WAVE_BITS-1:0]<=DATAC[WAVE_BITS-1:0];
end
endcase
end
always@(OUTC_2 or ADDOUTC_2)
case(OUTC_2[WAVE_BITS])
1'b0: OUTC_[WAVE_BITS:0]<=OUTC_2[WAVE_BITS:0];
1'b1: OUTC_[WAVE_BITS:0]<=ADDOUTC_2; //OUTS_ and OUTC_ are 2'complement datas.
endcase
always@(OUTS_2 or ADDOUTS_2)
case(OUTS_2[WAVE_BITS])
1'b0: OUTS_[WAVE_BITS:0]<=OUTS_2[WAVE_BITS:0];
1'b1: OUTS_[WAVE_BITS:0]<=ADDOUTS_2; //OUTS_ and OUTC_ are 2'complement datas.
endcase
addo U_addo(
.dataa(OUTS_1),
.result(ADDOUTS_1));
addo U1_addo(
.dataa(OUTC_1),
.result(ADDOUTC_1));
endmodule
`timescale 1 ns / 1 ns
module mult (
dataa,
datab,
clock,
result);
input [6:0] dataa;
input [7:0] datab;
input clock;
output [7:0] result;
reg [6:0] reg_a;
reg [7:0] reg_b;
wire [14:0] mult;
reg [7:0] result;
assign mult=reg_a*reg_b;
always@(posedge clock)
begin
reg_a<=dataa;
reg_b<=datab;
result<=mult[14:7]; //tow pipline
end
endmodule
`timescale 1 ns / 1 ns
module add (
dataa,
datab,
cin,
clock,
result);
input [12:0] dataa;
input [12:0] datab;
input cin;
input clock;
output [12:0] result;
reg[12:0] result;
wire[12:0] result1,wad;
assign wad=dataa+datab;
assign result1=wad+cin;
always@(posedge clock)
begin
result<=result1;
end
endmodule
`timescale 1 ns / 1 ns
module sub (
dataa,
datab,
cin,
clock,
result);
input [12:0] dataa;
input [12:0] datab;
input cin;
input clock;
output [12:0] result;
reg[12:0] result;
wire[12:0] wsub,result1;
assign wsub=dataa-datab;
assign result1=wsub-cin;
always@(posedge clock)
begin
result<=result1;
end
endmodule
`timescale 1 ns / 1 ns
module addo (
dataa,
result);
input [13:0] dataa;
output [13:0] result;
wire [13:0] result;
assign result=dataa+14'h0001;
endmodule
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