dds2ch.v

一种基于LUT的预失真方法。其中的一部分

//###############################################################################
// packed by packSrc.m version 0.2
// Date 27-Jul-2007 12:45:52 
// packed file list
//     dds2ch.v 
//     accl.v 
//     bctrl.v 
//     inverter.v 
//     romcl.v 
//     romwl.v 
//     mux.v 
//     muad.v 
//     tout.v 
//     mult.v 
//     add.v 
//     sub.v 
//     addo.v 
//################################################################################
`timescale 1ns/1ns

module dds2ch(
FREQWORD,          //input frequency word.
FREQEN,
CLK,
RESET,            //input reset signal.
OCLK,  
DSTA,
OUTPUTS,           //output sinwave data send to D/A.
OUTPUTC);          //output coswave data send to D/A.
      
// frequency word length
parameter  FREQ_BITS      =32; 
//output data word length
parameter  DATA_BITS      =14;
//useful bit word length (m+n+3)bits
parameter  U_BITS         =17;
//data/coefficient ROM address bit
parameter  ADDR_M         =7;
//interpolatin address n bit
parameter  ADDR_N         =7;
//Wordlength of Wave value,k bits 
parameter WAVE_BITS       =13;
//Wordlength of coefficients value,i bits 
parameter COEFF_BITS      =8;
//interpolation data wordlength j=ceil(log2(2pi(2^n-1)/2^(n+m+3)(2^k-1))).(n+i-n)
parameter INTER_BITS      =7; 


input                      RESET,CLK,FREQEN;
input[FREQ_BITS-1:0]       FREQWORD;
output[DATA_BITS-1:0]      OUTPUTS,OUTPUTC;
output                     OCLK,DSTA;

wire[U_BITS-1:0]           ubit;
wire                       OCLK,DSTA,ctl1,ctl2,ctl3,ctl4,octl2;
wire[ADDR_M-1:0]           addrm;
wire[ADDR_N-1:0]           addrn;
wire[WAVE_BITS-1:0]        w1,w2,outs,outc;
wire[COEFF_BITS-1:0]       c1,c2;
wire[DATA_BITS-1:0]        OUTPUTS,OUTPUTC;
wire[WAVE_BITS+WAVE_BITS-1:0] dataw;
wire[COEFF_BITS+COEFF_BITS-1:0] datac;


accl U_accl(
.FREQ(FREQWORD),           //input frequency word.
.FREQEN(FREQEN),
.RESET(RESET),           //input reset signal.
.CLK(CLK),                 //system clock.
.DATAEN(DSTA),
.UBITS(ubit));             //used bits in 32bits phase bit.

defparam  U_accl.FREQ_BITS=FREQ_BITS; 
defparam  U_accl.U_BITS=U_BITS;


bctrl U_bctrl(
.CLK(CLK),                 //System clock.
.RESET(RESET),
.INUBITS(ubit),            //input phasebits.
.CTL1(ctl1),               //3rd MSB.Control the inverter.
.CTL2(ctl2),               //2nd xor 3rd MSB.Control the sin/cos rom data output
.CTL3(ctl3),               //1st MSB.Sign bit of the sin output data.
.CTL4(ctl4));              //1st MSB.Sign bit of the cos output data.

defparam  U_bctrl.U_BITS=U_BITS;

inverter U_inverter(
.CTL(ctl1),                //ctl1
.UBITS1(ubit),             //m+n+3 bits input phase bit.
.ADDRM(addrm),             //m bits ROM address.
.ADDRN(addrn));            //n bits interpolation address.

defparam  U_inverter.U_BITS=U_BITS;
defparam  U_inverter.ADDR_M=ADDR_M;
defparam  U_inverter.ADDR_N=ADDR_N;

romwl U_romwl(
.SYSCLK(CLK),              // system clock
.ADDRESS(addrm),           // input address
.DATAW(dataw));            // output 1/8 sine and cos wave value,without sign bit,

defparam  U_romwl.ROM_BITS=ADDR_M;
defparam  U_romwl.WAVE_BITS=WAVE_BITS;


romcl U_romcl(
.SYSCLK(CLK),              // system clock
.ADDRESS(addrm),           // input address
.DATAC(datac));            // output 1/8 sine and cos coefficients data value,without sign bit,


defparam    U_romcl.ROM_BITS=ADDR_M;
defparam    U_romcl.COEFF_BITS=COEFF_BITS;

mux U_mux(
.RESET(RESET),           //system reset.
.CLK(CLK),                 //system clock.
.CTL2(ctl2),               //mux1~4's control bit.
.DATAW(dataw),             //input sine and cos ROM data.
.DATAC(datac),             //input sine and cos coefficient data.
.OCTL2(octl2),
.W1(w1),                   //output sin wave.  mux1 output.
.W2(w2),                   //output cos wave.       mux3 output.
.C1(c1),                   //output sin coefficient.mux2 output.
.C2(c2));                  //output cos coefficient.mux4 output.

defparam    U_mux.WAVE_BITS=WAVE_BITS;
defparam    U_mux.COEFF_BITS=COEFF_BITS;

muad U_muad(
.RESET(RESET),
.CLK(CLK),                 //system clock.
.CTL2(octl2),              //control add or sub
.W1(w1),                   //wave value input,from the mux1.
.W2(w2),                   //wave value input,from the mux3.
.C1(c1),                   //coefficient input,from the mux2.
.C2(c2),                   //coefficient input,from the mux4.
.ADDRN(addrn),             //interpolation address.
.OUTS(outs),               //k bits output sin wave data,without signed bit.
.OUTC(outc));              //k bits output cos wave data,without signed bit.

defparam  U_muad.WAVE_BITS=WAVE_BITS;
defparam  U_muad.COEFF_BITS=COEFF_BITS;
defparam  U_muad.INTER_BITS=INTER_BITS; 
defparam  U_muad.ADDR_N=ADDR_N;

out U_out(
.RESET(RESET),
.CLK(CLK),                 //system clk.
.OCLK(OCLK),
.CTL3(ctl3),               //sin wave sign bit.
.CTL4(ctl4),               //cos wave sign bit.
.DATAS(outs),              //sin wave value.
.DATAC(outc),              //cos wave value.
.OUTS(OUTPUTS),            //sinwave value with signed bit.
.OUTC(OUTPUTC));           //coswave value with signed bit.

defparam  U_out.WAVE_BITS=WAVE_BITS;


endmodule

module accl(
FREQ,           //input frequency word.
FREQEN,
RESET,           //input reset signal.
CLK,            //system clock.
DATAEN,
UBITS);         //used bits in 32bits phase bit.

// frequency word length
parameter  FREQ_BITS      =0; 
//useful bit word length (m+n+3)bits
parameter  U_BITS         =0;

input                   RESET,CLK,FREQEN;
input[FREQ_BITS-1:0]    FREQ;
output                  DATAEN;
output[U_BITS-1:0]      UBITS;

wire[FREQ_BITS-1:0]     a,wFREQ; 
reg[FREQ_BITS-1:0]      phout,rFREQ,r1FREQ;
reg                     DATAEN,r11DATAEN,r10DATAEN,r9DATAEN,r8DATAEN,r7DATAEN,r6DATAEN,r5DATAEN,r4DATAEN,r3DATAEN,r2DATAEN,r1DATAEN;

assign UBITS[U_BITS-1:0]=phout[FREQ_BITS-1:FREQ_BITS-U_BITS];
assign a=phout;
assign wFREQ=rFREQ;

always@(posedge CLK or posedge RESET)
begin
	if(RESET)
        begin
		    r1FREQ<=0;
            rFREQ<=0;
        end
	else 
        begin
	    	r1FREQ<=rFREQ;
            if(FREQEN)
                rFREQ<=FREQ;
	        else
                rFREQ<=wFREQ;
        end
end       
         
always@(posedge CLK or posedge RESET)
begin          
    if(RESET)
        begin
            DATAEN<=0;
            r1DATAEN<=0;
            r2DATAEN<=0;
            r3DATAEN<=0;
            r4DATAEN<=0;
            r5DATAEN<=0;
            r6DATAEN<=0;
            r7DATAEN<=0;
            r8DATAEN<=0;
            r9DATAEN<=0;
            r10DATAEN<=0;
            r11DATAEN<=0;
        end
    else 
        begin
            if(r1FREQ!=rFREQ)
                r1DATAEN<=1;
            else
                r1DATAEN<=0;
        r2DATAEN<=r1DATAEN;
        r3DATAEN<=r2DATAEN;
        r4DATAEN<=r3DATAEN;
        r5DATAEN<=r4DATAEN;
        r6DATAEN<=r5DATAEN;
        r7DATAEN<=r6DATAEN;
        r8DATAEN<=r7DATAEN;
        r9DATAEN<=r8DATAEN;
        r10DATAEN<=r9DATAEN;
        r11DATAEN<=r10DATAEN;
        DATAEN<=r11DATAEN;
        end
end

always@(posedge CLK or posedge RESET)
begin
    if(RESET)
    begin
        phout<=0;
    end
    else
    begin
        phout<=a+rFREQ;
    
    end    

end




endmodule
module bctrl(
CLK,          //System clock.
RESET,
INUBITS,      //input phasebits.
CTL1,         //3rd MSB.Control the inverter.
CTL2,         //2nd xor 3rd MSB.Control the sin/cos rom data output
CTL3,         //1st MSB.Sign bit of the sin output data.
CTL4);        //1st MSB.Sign bit of the cod output data.

//useful bit word length (m+n+3)bits
parameter  U_BITS         =0;
input               CLK,RESET;
input[U_BITS-1:0]   INUBITS;
output              CTL1,CTL2,CTL3,CTL4;

reg                 CTL2,CTL2_,CTL3,CTL4,CTL3_1,CTL4_1,CTL3_2,CTL4_2,CTL3_3,CTL4_3,CTL3_4,CTL4_4,CTL3_5,CTL4_5,CTL3_6,CTL4_6,CTL3_7,CTL4_7;
wire                CTL1,nd2;



assign nd2=INUBITS[U_BITS-2];
assign CTL1=INUBITS[U_BITS-3];

always@(posedge CLK or posedge RESET)
begin
    if(RESET)
    begin
        CTL2_<=0;
        CTL3_1<=0;
        CTL3_2<=0;
        CTL3_3<=0;
        CTL3_4<=0;
        CTL3_5<=0;
        CTL3_6<=0;
        CTL3_7<=0;
        CTL4_1<=0;
        CTL4_2<=0;
        CTL4_3<=0;
        CTL4_4<=0;
        CTL4_5<=0;
        CTL4_6<=0;
        CTL4_7<=0;
        CTL2<=0;
        CTL3<=0;
        CTL4<=0;
    end
    else
    begin
        CTL2_<=CTL1^nd2;
        CTL2<=CTL2_;                               //CTL2 delayl two periodic
        CTL3_1<=INUBITS[U_BITS-1];        
        CTL4_1<=(INUBITS[(U_BITS-1)]^nd2);         //CTL3,CTL4 delayl 4 periodics
        CTL3_2<=CTL3_1;
        CTL4_2<=CTL4_1;
        CTL3_3<=CTL3_2;
        CTL4_3<=CTL4_2;
        CTL3_4<=CTL3_3;
        CTL4_4<=CTL4_3;
        CTL3_5<=CTL3_4;
        CTL4_5<=CTL4_4;
        CTL3_6<=CTL3_5;
        CTL4_6<=CTL4_5;
        CTL3_7<=CTL3_6;
        CTL4_7<=CTL4_6;
        CTL3<=CTL3_7;
        CTL4<=CTL4_7;
    end
end

endmodule


module inverter(
CTL,              //ctl1
UBITS1,           //m+n+3 bits input phase bit.
ADDRM,            //m bits ROM address.
ADDRN);           //n bits interpolation address.


//useful bit word length (m+n+3)bits
parameter  U_BITS         =0;
//data/coefficient ROM address bit
parameter  ADDR_M         =0;
//interpolatin address bit
parameter  ADDR_N         =0;

input                    CTL;
input[U_BITS-1:0]        UBITS1;
output[ADDR_M-1:0]       ADDRM;
output[ADDR_N-1:0]       ADDRN;

reg[ADDR_M+ADDR_N-1:0]   inv_out,inv_t;

wire[ADDR_M+ADDR_N-1:0]  inv_in;
wire[ADDR_M-1:0]         ADDRM;
wire[ADDR_N-1:0]         ADDRN;


assign inv_in[ADDR_M+ADDR_N-1:0]=UBITS1[U_BITS-4:0];
assign ADDRM[ADDR_M-1:0]=inv_out[ADDR_M+ADDR_N-1:ADDR_N];
assign ADDRN[ADDR_N-1:0]=inv_out[ADDR_N-1:0];



always@(CTL or inv_in)
case(CTL)
	1'b1:  inv_out<=~inv_in;   
    1'b0:  inv_out<=inv_in;
endcase


endmodule

module romcl(
   SYSCLK,      // system clock
   ADDRESS,     // input address
   DATAC);      // output 1/8 sine and cos coefficients data value,the higher COEFF_BITS bits is sine coefficinet data,the lower bits is cos coeeficient data.
   
//Data ROM's address bit.  m bits
parameter ROM_BITS     =0 ;
//Wordlength of coefficients value,i bits 
parameter COEFF_BITS    =0;
 
input                               SYSCLK;
input[ROM_BITS-1:0]                 ADDRESS;
output[COEFF_BITS+COEFF_BITS-1:0]   DATAC;

reg[COEFF_BITS+COEFF_BITS-1:0]      data,DATAC; 

  
  always@(ADDRESS)
    case(ADDRESS)
      //`include "romdata2.v"
7'h0: data=16'h0065;
7'h1: data=16'h0065;
7'h2: data=16'h0165;
7'h3: data=16'h0265;
7'h4: data=16'h0265;
7'h5: data=16'h0365;
7'h6: data=16'h0365;
7'h7: data=16'h0465;
7'h8: data=16'h0565;
7'h9: data=16'h0565;
7'ha: data=16'h0665;
7'hb: data=16'h0765;
7'hc: data=16'h0765;
7'hd: data=16'h0865;
7'he: data=16'h0865;
7'hf: data=16'h0965;
7'h10: data=16'h0a65;
7'h11: data=16'h0a65;
7'h12: data=16'h0b65;
7'h13: data=16'h0b65;
7'h14: data=16'h0c65;
7'h15: data=16'h0d64;
7'h16: data=16'h0d64;
7'h17: data=16'h0e64;
7'h18: data=16'h0f64;
7'h19: data=16'h0f64;
7'h1a: data=16'h1064;
7'h1b: data=16'h1064;
7'h1c: data=16'h1164;
7'h1d: data=16'h1264;
7'h1e: data=16'h1264;
7'h1f: data=16'h1363;
7'h20: data=16'h1363;
7'h21: data=16'h1463;
7'h22: data=16'h1563;
7'h23: data=16'h1563;
7'h24: data=16'h1663;
7'h25: data=16'h1763;
7'h26: data=16'h1762;
7'h27: data=16'h1862;
7'h28: data=16'h1862;
7'h29: data=16'h1962;
7'h2a: data=16'h1a62;
7'h2b: data=16'h1a62;
7'h2c: data=16'h1b62;
7'h2d: data=16'h1b61;
7'h2e: data=16'h1c61;
7'h2f: data=16'h1d61;
7'h30: data=16'h1d61;
7'h31: data=16'h1e61;
7'h32: data=16'h1e60;
7'h33: data=16'h1f60;
7'h34: data=16'h1f60;
7'h35: data=16'h2060;
7'h36: data=16'h2160;
7'h37: data=16'h215f;
7'h38: data=16'h225f;
7'h39: data=16'h225f;
7'h3a: data=16'h235f;
7'h3b: data=16'h245f;
7'h3c: data=16'h245e;
7'h3d: data=16'h255e;
7'h3e: data=16'h255e;
7'h3f: data=16'h265e;
7'h40: data=16'h265d;
7'h41: data=16'h275d;
7'h42: data=16'h285d;
7'h43: data=16'h285d;
7'h44: data=16'h295c;
7'h45: data=16'h295c;
7'h46: data=16'h2a5c;
7'h47: data=16'h2a5c;
7'h48: data=16'h2b5b;
7'h49: data=16'h2c5b;
7'h4a: data=16'h2c5b;
7'h4b: data=16'h2d5b;
7'h4c: data=16'h2d5a;
7'h4d: data=16'h2e5a;
7'h4e: data=16'h2e5a;
7'h4f: data=16'h2f59;
7'h50: data=16'h2f59;
7'h51: data=16'h3059;
7'h52: data=16'h3159;
7'h53: data=16'h3158;
7'h54: data=16'h3258;
7'h55: data=16'h3258;
7'h56: data=16'h3357;
7'h57: data=16'h3357;
7'h58: data=16'h3457;
7'h59: data=16'h3456;
7'h5a: data=16'h3556;
7'h5b: data=16'h3556;
7'h5c: data=16'h3655;
7'h5d: data=16'h3655;
7'h5e: data=16'h3755;
7'h5f: data=16'h3854;
7'h60: data=16'h3854;
7'h61: data=16'h3954;
7'h62: data=16'h3953;
7'h63: data=16'h3a53;
7'h64: data=16'h3a53;
7'h65: data=16'h3b52;
7'h66: data=16'h3b52;
7'h67: data=16'h3c52;
7'h68: data=16'h3c51;
7'h69: data=16'h3d51;
7'h6a: data=16'h3d50;
7'h6b: data=16'h3e50;
7'h6c: data=16'h3e50;
7'h6d: data=16'h3f4f;
7'h6e: data=16'h3f4f;
7'h6f: data=16'h404f;
7'h70: data=16'h404e;
7'h71: data=16'h414e;
7'h72: data=16'h414d;
7'h73: data=16'h414d;
7'h74: data=16'h424d;
7'h75: data=16'h424c;
7'h76: data=16'h434c;
7'h77: data=16'h434b;
7'h78: data=16'h444b;
7'h79: data=16'h444a;
7'h7a: data=16'h454a;
7'h7b: data=16'h454a;
7'h7c: data=16'h4649;
7'h7d: data=16'h4649;
7'h7e: data=16'h4748;
7'h7f: data=16'h4748;
      default:  data = 0;                    
    endcase
    
  always@(posedge SYSCLK)
    begin
        DATAC<=data;
    end
endmodule

module romwl(
   SYSCLK,      // system clock
   ADDRESS,     // input address
   DATAW);      // output 1/8 sine and cos wave value,without sign bit.The higher WAVE_BITS is the sin wave data,the lower bits is the cos wave data.
   
//Data ROM's address bit.  m bits
parameter ROM_BITS    = 0;
//Wordlength of Wave value,k bits 
parameter WAVE_BITS    = 0;
 
input                             SYSCLK;
input[ROM_BITS-1:0]               ADDRESS;
output[WAVE_BITS+WAVE_BITS-1:0]   DATAW;

reg[WAVE_BITS+WAVE_BITS-1:0]      data,DATAW; 

  
always@(ADDRESS)
    case(ADDRESS)

7'h0: data=26'h3ffe000;
7'h1: data=26'h3ffe032;
7'h2: data=26'h3ffc065;
7'h3: data=26'h3ffc097;
7'h4: data=26'h3ffa0c9;
7'h5: data=26'h3ff60fb;
7'h6: data=26'h3ff212d;
7'h7: data=26'h3fee160;
7'h8: data=26'h3fea192;
7'h9: data=26'h3fe61c4;
7'ha: data=26'h3fe01f6;
7'hb: data=26'h3fd8228;
7'hc: data=26'h3fd225b;
7'hd: data=26'h3fca28d;
7'he: data=26'h3fc22bf;
7'hf: data=26'h3fb82f1;
7'h10: data=26'h3fb0323;
7'h11: data=26'h3fa4355;
7'h12: data=26'h3f9a387;
7'h13: data=26'h3f8e3b9;
7'h14: data=26'h3f823eb;
7'h15: data=26'h3f7641d;
7'h16: data=26'h3f6844e;
7'h17: data=26'h3f5c480;
7'h18: data=26'h3f4c4b2;
7'h19: data=26'h3f3e4e4;
7'h1a: data=26'h3f2e515;
7'h1b: data=26'h3f1e547;
7'h1c: data=26'h3f0c578;
7'h1d: data=26'h3efc5aa;
7'h1e: data=26'h3eea5db;
7'h1f: data=26'h3ed660d;
7'h20: data=26'h3ec463e;
7'h21: data=26'h3eb066f;
7'h22: data=26'h3e9a6a0;
7'h23: data=26'h3e866d2;
7'h24: data=26'h3e70703;
7'h25: data=26'h3e5a734;
7'h26: data=26'h3e42765;
7'h27: data=26'h3e2c795;
7'h28: data=26'h3e147c6;
7'h29: data=26'h3dfa7f7;
7'h2a: data=26'h3de2828;
7'h2b: data=26'h3dc8858;
7'h2c: data=26'h3dac889;
7'h2d: data=26'h3d928b9;
7'h2e: data=26'h3d768e9;
7'h2f: data=26'h3d5a91a;
7'h30: data=26'h3d3c94a;
7'h31: data=26'h3d2097a;
7'h32: data=26'h3d029aa;
7'h33: data=26'h3ce29da;
7'h34: data=26'h3cc4a09;
7'h35: data=26'h3ca4a39;
7'h36: data=26'h3c82a69;