mod.v

来自「一种基于LUT的预失真方法。其中的一部分」· Verilog 代码 · 共 58 行

/*
module mod(ibase,qbase,qtran,itran,clk,rstn,rf);
input   signed  [15:0] ibase,qbase;
input   signed  [13:0] itran,qtran;
input   clk,rstn;
output  [11:0] rf;

reg     signed  [29:0] lposition,rposition;
reg		signed  [30:0] rfout;

assign	rf = {~rfout[30],rfout[26:16]};
always@(posedge clk or negedge rstn)
	if (!rstn)
		rfout <= 18'h0;
	else
		begin	
			lposition <= ibase*qtran;
			rposition <= qbase*itran;
			rfout <= {lposition[29],lposition} + {rposition[29],rposition};   
		end
endmodule
*/



module mod(ibase,qbase,qtran,itran,clk,rstn,rf);
input   signed  [15:0] ibase,qbase;
input   signed  [13:0] itran,qtran;
input   signed  clk,rstn;

output  [11:0] rf;

reg     signed  [17:0] lposition,rposition;
wire    signed  [11:0] rf;

reg		signed  [18:0] rfout;
wire	signed	[8:0] a,b,c,d;

assign	a = {ibase[15],ibase[14:7]};
assign	b = {qbase[15],qbase[14:7]};
assign	c = itran[13:5];
assign	d = qtran[13:5];

assign	rf = {~rfout[18],rfout[17:7]};
always@(posedge clk or negedge rstn)
	if (!rstn)
		rfout <= 18'h0;
	else
		begin	
			lposition <= a*d;
			rposition <= b*c;
			rfout <= {lposition[17],lposition} + {rposition[17],rposition}; 
//			rfout <= lposition + rposition;   
		end
endmodule