fifo.twr

verilog source code for uart design

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Release 8.2i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

C:\Xilinx\bin\nt\trce.exe -ise C:/Xilinx/digi/lab3/lab3.ise -intstyle ise -e 3
-l 3 -s 12 -xml FIFO FIFO.ncd -o FIFO.twr FIFO.pcf

Design file:              fifo.ncd
Physical constraint file: fifo.pcf
Device,speed:             xc4vlx100,-12 (PRODUCTION 1.60 2006-05-03, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
data<0>     |   -0.782(R)|    2.888(R)|clk_BUFGP         |   0.000|
data<1>     |   -0.518(R)|    2.968(R)|clk_BUFGP         |   0.000|
data<2>     |    0.368(R)|    2.563(R)|clk_BUFGP         |   0.000|
data<3>     |    0.309(R)|    2.703(R)|clk_BUFGP         |   0.000|
rd          |    1.051(R)|    2.488(R)|clk_BUFGP         |   0.000|
reset       |    0.300(R)|    1.904(R)|clk_BUFGP         |   0.000|
wr          |    4.884(R)|   -0.104(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
data1<0>    |    7.569(R)|clk_BUFGP         |   0.000|
data1<1>    |    7.562(R)|clk_BUFGP         |   0.000|
data1<2>    |    7.578(R)|clk_BUFGP         |   0.000|
data1<3>    |    7.570(R)|clk_BUFGP         |   0.000|
empty       |    8.858(R)|clk_BUFGP         |   0.000|
full        |    9.370(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    4.429|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Tue Feb 03 16:19:27 2009
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Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 299 MB