fifo.bld

verilog source code for uart design

Release 8.2i ngdbuild I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

Command Line: C:\Xilinx\bin\nt\ngdbuild.exe -ise C:/Xilinx/digi/lab3/lab3.ise
-intstyle ise -dd _ngo -nt timestamp -i -p xc4vlx100-ff1148-12 FIFO.ngc FIFO.ngd

Reading NGO file 'C:/Xilinx/digi/lab3/FIFO.ngc' ...

Checking timing specifications ...
Checking Partitions ...
Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 84544 kilobytes

Writing NGD file "FIFO.ngd" ...

Writing NGDBUILD log file "FIFO.bld"...