hdpdeps.ref

verilog source code for uart design

V3 9
FL $XILINX/digi/lab3/FIFO.v 2009/02/03.15:56:11 I.31
MO isim_temp/FIFO       FL $XILINX/digi/lab3/FIFO.v
FL $XILINX/digi/lab3/test1.v 2009/02/03.14:53:43 I.31
MO isim_temp/test1      FL $XILINX/digi/lab3/test1.v
FL $XILINX/digi/lab3/testfifo.v 2009/02/03.15:54:56 I.31
MO isim_temp/testfifo   FL $XILINX/digi/lab3/testfifo.v MI FIFO
FL $XILINX/verilog/src/glbl.v 2006/05/17.23:39:08 I.31
MO isim_temp/glbl       FL $XILINX/verilog/src/glbl.v