hdllib.ref

verilog source code for uart design

MO FIFO NULL C:\Xilinx\digi\lab3/FIFO.v vlg7C/_f_i_f_o.bin 1233656772
MO test1 NULL C:\Xilinx\digi\lab3/test1.v vlg35/test1.bin 1233653024
MO testfifo NULL C:\Xilinx\digi\lab3/testfifo.v vlg70/testfifo.bin 1233656772
MO glbl NULL C:/Xilinx/verilog/src/glbl.v vlg2D/glbl.bin 1233656772