hdpdeps.ref

来自「verilog source code for uart design」· REF 代码 · 共 10 行

V3 9
FL $XILINX/digi/lab3/FIFO.v 2009/02/03.15:56:11 I.31
MO work/FIFO            FL $XILINX/digi/lab3/FIFO.v
FL $XILINX/digi/lab3/test1.v 2009/02/03.14:53:43 I.31
MO work/test1           FL $XILINX/digi/lab3/test1.v
FL $XILINX/digi/lab3/testfifo.v 2009/02/03.15:54:56 I.31
MO work/testfifo        FL $XILINX/digi/lab3/testfifo.v MI FIFO
FL $XILINX/verilog/src/glbl.v 2006/05/17.23:39:08 I.31
MO work/glbl            FL $XILINX/verilog/src/glbl.v