da_tlc5620.map.rpt

用verilong hdl语言编写的数据采样程序

; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone                                  ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM Block Balancing                                           ; On                 ; On                 ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                               ; Unlimited          ; Unlimited          ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Maximum Number of M-RAM Memory Blocks                              ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                             ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                   ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------+
; DA_TLC5620.v                     ; yes             ; User Verilog HDL File        ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DA_TLC5620.v               ;
; dac_test.v                       ; yes             ; User Verilog HDL File        ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v                 ;
; tlc5620.v                        ; yes             ; Other                        ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/tlc5620.v                  ;
; DISPLAY.v                        ; yes             ; Other                        ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v                  ;
; lpm_mult.tdf                     ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf                       ;
; aglobal60.inc                    ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/aglobal60.inc                      ;
; lpm_add_sub.inc                  ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.inc                    ;
; multcore.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/multcore.inc                       ;
; bypassff.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/bypassff.inc                       ;
; altshift.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altshift.inc                       ;
; multcore.tdf                     ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/multcore.tdf                       ;
; csa_add.inc                      ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/csa_add.inc                        ;
; mpar_add.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/mpar_add.inc                       ;
; muleabz.inc                      ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/muleabz.inc                        ;
; mul_lfrg.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/mul_lfrg.inc                       ;
; mul_boothc.inc                   ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/mul_boothc.inc                     ;
; alt_ded_mult.inc                 ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/alt_ded_mult.inc                   ;
; alt_ded_mult_y.inc               ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/alt_ded_mult_y.inc                 ;
; dffpipe.inc                      ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/dffpipe.inc                        ;
; mpar_add.tdf                     ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/mpar_add.tdf                       ;
; lpm_add_sub.tdf                  ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf                    ;
; addcore.inc                      ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/addcore.inc                        ;
; look_add.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/look_add.inc                       ;
; alt_stratix_add_sub.inc          ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/alt_stratix_add_sub.inc            ;
; alt_mercury_add_sub.inc          ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/alt_mercury_add_sub.inc            ;
; addcore.tdf                      ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/addcore.tdf                        ;
; a_csnbuffer.inc                  ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.inc                    ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf                    ;
; altshift.tdf                     ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/altshift.tdf                       ;
; lpm_divide.tdf                   ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf                     ;
; abs_divider.inc                  ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/abs_divider.inc                    ;
; sign_div_unsign.inc              ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/sign_div_unsign.inc                ;
; db/lpm_divide_tul.tdf            ; yes             ; Auto-Generated Megafunction  ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/lpm_divide_tul.tdf      ;
; db/sign_div_unsign_mlh.tdf       ; yes             ; Auto-Generated Megafunction  ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/sign_div_unsign_mlh.tdf ;
; db/alt_u_div_sqe.tdf             ; yes             ; Auto-Generated Megafunction  ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/alt_u_div_sqe.tdf       ;
; db/add_sub_3dc.tdf               ; yes             ; Auto-Generated Megafunction  ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_3dc.tdf         ;
; db/add_sub_4dc.tdf               ; yes             ; Auto-Generated Megafunction  ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_4dc.tdf         ;
; db/add_sub_7dc.tdf               ; yes             ; Auto-Generated Megafunction  ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_7dc.tdf         ;
; db/add_sub_5dc.tdf               ; yes             ; Auto-Generated Megafunction  ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_5dc.tdf         ;
; db/add_sub_6dc.tdf               ; yes             ; Auto-Generated Megafunction  ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_6dc.tdf         ;
; db/add_sub_59c.tdf               ; yes             ; Auto-Generated Megafunction  ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_59c.tdf         ;
; db/lpm_divide_q6m.tdf            ; yes             ; Auto-Generated Megafunction  ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/lpm_divide_q6m.tdf      ;
; db/lpm_divide_t6m.tdf            ; yes             ; Auto-Generated Megafunction  ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/lpm_divide_t6m.tdf      ;
; db/sign_div_unsign_plh.tdf       ; yes             ; Auto-Generated Megafunction  ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/sign_div_unsign_plh.tdf ;
; db/alt_u_div_2re.tdf             ; yes             ; Auto-Generated Megafunction  ; E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/alt_u_div_2re.tdf       ;