da_tlc5620.map.rpt

用verilong hdl语言编写的数据采样程序

Analysis & Synthesis report for DA_TLC5620
Thu Nov 27 19:35:44 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |DA_TLC5620|DISPLAY:M3|state
  8. State Machine - |DA_TLC5620|DISPLAY:M3|shift_state
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Multiplexer Restructuring Statistics (Restructuring Performed)
 12. Parameter Settings for User Entity Instance: tlc5620:M1
 13. Parameter Settings for User Entity Instance: dac_test:M2
 14. Parameter Settings for User Entity Instance: DISPLAY:M3
 15. Parameter Settings for Inferred Entity Instance: dac_test:M2|lpm_mult:Mult0
 16. Parameter Settings for Inferred Entity Instance: dac_test:M2|lpm_divide:Mod0
 17. Parameter Settings for Inferred Entity Instance: dac_test:M2|lpm_divide:Div0
 18. Parameter Settings for Inferred Entity Instance: dac_test:M2|lpm_divide:Mod1
 19. Parameter Settings for Inferred Entity Instance: dac_test:M2|lpm_divide:Div1
 20. Parameter Settings for Inferred Entity Instance: dac_test:M2|lpm_divide:Mod2
 21. Parameter Settings for Inferred Entity Instance: dac_test:M2|lpm_divide:Div2
 22. Parameter Settings for Inferred Entity Instance: dac_test:M2|lpm_divide:Mod3
 23. lpm_mult Parameter Settings by Entity Instance
 24. Analysis & Synthesis Messages
 25. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Nov 27 19:35:44 2008    ;
; Quartus II Version          ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name               ; DA_TLC5620                               ;
; Top-level Entity Name       ; DA_TLC5620                               ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 832                                      ;
; Total pins                  ; 11                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 0                                        ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP1C6Q240C8        ;                    ;
; Top-level entity name                                              ; DA_TLC5620         ; DA_TLC5620         ;
; Family name                                                        ; Cyclone            ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;