display.v

用verilong hdl语言编写的数据采样程序

////////////////////////////////////////////////////////////////////////
//Company      : 伟杰电子                                             //                  
//Web address  : http://www.weijay.com                                //
//Engineer     : Jaylee                                               //
//QQ           : 54304441                                             //
//Email        : [e-mail]                                  //
//实验名称     ：CH451控制数码管显示实验                              //
//功能实现     ：以固定时钟周期让8个LED从0~9循环显示                  //
////////////////////////////////////////////////////////////////////////                                                     
//--------------------------system clk 50MHz-------------------------///

//*******************************************************************************
//dispaly_data[4:0]                 段G～段A                显示的字符
//    0_0000B                       0111111B                    0
//    0_0001B                       0000110B                    1
//    0_0010B                       1011011B                    2
//    0_0011B                       1001111B                    3
//    0_0100B                       1100110B                    4
//    0_0101B                       1101101B                    5
//    0_0110B                       1111101B                    6
//    0_0111B                       0000111B                    7
//    0_1000B                       1111111B                    8
//    0_1001B                       1101111B                    9
//    0_1010B                       1110111B                    A
//    0_1011B                       1111100B                    b
//    0_1100B                       1011000B                    c
//    0_1101B                       1011110B                    d
//    0_1110B                       1111001B                    E
//    0_1111B                       1110001B                    F
//******************************************************************************
//    1_0000B                       0000000B                   空格
//    1_0001B                       1000110B                    -1
//    1_0010B                       1000000B                    -
//    1_0011B                       1000001B                     =
//    1_0100B                       0111001B                    [
//    1_0101B                       0001111B                    ]
//    1_0110B                       0001000B                    _
//    1_0111B                       1110110B                    H
//    1_1000B                       0111000B                    L
//    1_1001B                       1110011B                    P
//    1_1010B                       0000000B                    .
//     其他                         0000000B                   空格
//*******************************************************************************


`timescale 1ns/1ns
`define CH451_RESET     12'h201 //cmd_rst
`define CH451_SYSON1    12'h401 //cmd_open_display
//`define CH451_SYSON2    12'h403 //cmd_open_display_scan
`define CH451_DSP       12'h500 //cmd_set_default_decode_mode
`define CH451_BCD       12'h580 //cmd_set_BCD_decode_mode
//`define CH451_KEY       12'h700 //cmd_read_keyvalue
module DISPLAY (
                clk,
                rst_n,
                data,
                CH451_DCLK,
                CH451_DIN,
                CH451_LOAD
               );
//reference define
parameter   clk_div_factor     = 4'b1001;         //5MHz serial clk generate factor
parameter   point_i            = 8'b0000_1000;    //decimal point select,'1'select
parameter   digit_on_num       = 4'b1000;         //the num of the LED used

//display top_cmd
parameter   CH451_DISPLAY  = 32'hf_e_d_c_b_a_9_8; //cmd_display the right LED

//define main state machine
parameter   CH451_Idle               = 9'b0_0000_0001;
parameter   CH451_Enable_serial_port = 9'b0_0000_0010;      
parameter   CH451_Reset              = 9'b0_0000_0100;
parameter   CH451_Set_display_mode   = 9'b0_0000_1000;
parameter   CH451_Open_display       = 9'b0_0001_0000;
parameter   CH451_Get_data           = 9'b0_0010_0000;
parameter   CH451_Display_ready      = 9'b0_0100_0000;
parameter   CH451_Display            = 9'b0_1000_0000;
parameter   CH451_Display_temp       = 9'b1_0000_0000;

//define shift state machine
parameter   Shift12_out_idle         = 7'b000_0001;
parameter   Pull_down_ch451_load     = 7'b000_0010;
parameter   Get_shift_out_data       = 7'b000_0100;
parameter   Pull_down_ch451_dclk     = 7'b000_1000;
parameter   Pull_up_ch451_dclk       = 7'b001_0000;
parameter   Shift_paralell_data      = 7'b010_0000;
parameter   Pull_up_ch451_load       = 7'b100_0000;


//input decaration
input                         clk;             //system clk
input                         rst_n;           //system rst,'0' valid
input [5*digit_on_num-1:0]    data;            //display data input
//output decaration
output                        CH451_DIN;       //ch451 serial input
output                        CH451_DCLK;      //ch451 serial input clk
output                        CH451_LOAD;      //ch451 data/cmd load

reg                           CH451_DIN;
reg                           CH451_DCLK;
reg                           CH451_LOAD;
//---------------------------define led display reg-----------------------
reg                           trans_over_flag;
reg [3:0]                     clk_div_counter;
reg [3:0]                     shift_counter;
reg [11:0]                    CH451_cmd;
reg [2:0]                     transfer_count;
reg [digit_on_num-1:0]        decemial_point_sel;
reg [4*digit_on_num-1:0]      display_led_sel;
reg [5*digit_on_num-1:0]      display_data;
reg [10:0]                    state;
reg [6:0]                     shift_state;

//clk divide for the main state machine
always @(posedge clk or negedge rst_n) begin //default factor=10 or 5MHz
  if(!rst_n) clk_div_counter<=0;
  else if(clk_div_counter==clk_div_factor) clk_div_counter<=0;
  else clk_div_counter<=clk_div_counter+1'b1;
end

//main state
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    state<=CH451_Idle;
	shift_state<=Shift12_out_idle;
    CH451_DIN<=1'b1;
    CH451_DCLK<=1'b1;
    CH451_LOAD<=1'b1;
    transfer_count<=0;
    shift_counter<=0;
	display_data<=0;          
    decemial_point_sel<=0;    
    display_led_sel<=0;       
	CH451_cmd<=12'h000;       
    trans_over_flag<=1'b0;
  end
  else if(clk_div_counter==clk_div_factor) begin
    case(state)
    CH451_Idle:begin
      CH451_DIN<=1'b0;
      state<=CH451_Enable_serial_port;
    end
    CH451_Enable_serial_port: begin
      CH451_DIN<=1'b1;
      trans_over_flag<=1'b0;
      CH451_cmd<=`CH451_RESET;
      state<=CH451_Reset;
    end
    CH451_Reset:begin
      if(trans_over_flag==1'b0)
        shift12_out;
      else begin
        trans_over_flag<=1'b0;
        CH451_cmd<=`CH451_BCD;
        state<=CH451_Set_display_mode;
      end
    end
    CH451_Set_display_mode:begin
      if(trans_over_flag==0)
        shift12_out;
      else begin
        trans_over_flag<=1'b0;
        CH451_cmd<=`CH451_SYSON1;
        state<=CH451_Open_display;
      end
    end
    CH451_Open_display:begin
      if(trans_over_flag==0)
        shift12_out;
      else begin
        trans_over_flag<=1'b0;
        state<=CH451_Get_data;
      end
    end
    CH451_Get_data:begin
      display_data[5*digit_on_num-1:0]<=data[5*digit_on_num-1:0];
      decemial_point_sel<=point_i[7:8-digit_on_num];
      display_led_sel<=CH451_DISPLAY[4*digit_on_num-1:0];
      state<=CH451_Display_ready;
    end
    CH451_Display_ready:begin
      CH451_cmd<={
	              display_led_sel[3:0],
                  decemial_point_sel[0],
                  2'b00,
                  display_data[4:0]
                 };
      state<=CH451_Display;
    end
    CH451_Display:begin
      if(trans_over_flag==0)
        shift12_out;
      else begin
        trans_over_flag<=1'b0;
        state<=CH451_Display_temp;
      end
    end
    CH451_Display_temp:begin
      if(transfer_count==digit_on_num-1) begin
		state<=CH451_Get_data;
        transfer_count<=0;
	  end
      else begin
        state<=CH451_Display_ready;
        transfer_count<=transfer_count+1'b1;
        display_data<={
		               display_data[4:0],
                       display_data[5*digit_on_num-1:5]
                      };
        decemial_point_sel<={
                             decemial_point_sel[0],
                             decemial_point_sel[digit_on_num-1:1]
                            };
        display_led_sel<={
                          display_led_sel[3:0],
                          display_led_sel[4*digit_on_num-1:4]
                         };
      end
    end
    default:state<=CH451_Idle;
    endcase
  end
end

//send the 12 bits display cmd to the CH451(12 bits shift register)
task shift12_out;
begin
  casex(shift_state)
  Shift12_out_idle:begin
    shift_state<=Pull_down_ch451_load;
  end
  Pull_down_ch451_load:begin
    shift_state<=Get_shift_out_data;
    CH451_LOAD<=1'b0;
  end
  Get_shift_out_data:begin
    shift_state<=Pull_down_ch451_dclk;
    CH451_DIN<=CH451_cmd[0];
  end
  Pull_down_ch451_dclk:begin
    CH451_DCLK<=1'b0;
    shift_state<=Pull_up_ch451_dclk;
  end
  Pull_up_ch451_dclk:begin
    CH451_DCLK<=1'b1;
    shift_state<=Shift_paralell_data;
  end
  Shift_paralell_data:begin
    if(shift_counter==11)begin
	  shift_state<=Pull_up_ch451_load;
	  shift_counter<=0;
	end
    else begin
      shift_counter<=shift_counter+1'b1;
      CH451_cmd<={1'b0,CH451_cmd[11:1]};
      shift_state<=Get_shift_out_data;
    end
  end
  Pull_up_ch451_load:begin
    trans_over_flag<=1'b1;
    shift_state<=Shift12_out_idle;
    CH451_LOAD<=1'b1;
  end
  default:begin
    shift_state<=Shift12_out_idle;
	end
  endcase
end
endtask
   
endmodule