da_tlc5620.map.qmsg

用verilong hdl语言编写的数据采样程序

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_plh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_plh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_plh " "Info: Found entity 1: sign_div_unsign_plh" {  } { { "db/sign_div_unsign_plh.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/sign_div_unsign_plh.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_2re.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_2re.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_2re " "Info: Found entity 1: alt_u_div_2re" {  } { { "db/alt_u_div_2re.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/alt_u_div_2re.tdf" 38 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_adc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_adc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_adc " "Info: Found entity 1: add_sub_adc" {  } { { "db/add_sub_adc.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_adc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_8dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_8dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_8dc " "Info: Found entity 1: add_sub_8dc" {  } { { "db/add_sub_8dc.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_8dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_9dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_9dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_9dc " "Info: Found entity 1: add_sub_9dc" {  } { { "db/add_sub_9dc.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_9dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_89c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_89c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_89c " "Info: Found entity 1: add_sub_89c" {  } { { "db/add_sub_89c.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_89c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dac_test:M2\|lpm_divide:Div2 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_divide:Div2\"" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 98 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_78m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_78m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_78m " "Info: Found entity 1: lpm_divide_78m" {  } { { "db/lpm_divide_78m.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/lpm_divide_78m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_3nh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_3nh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_3nh " "Info: Found entity 1: sign_div_unsign_3nh" {  } { { "db/sign_div_unsign_3nh.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/sign_div_unsign_3nh.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_mte.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_mte.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_mte " "Info: Found entity 1: alt_u_div_mte" {  } { { "db/alt_u_div_mte.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/alt_u_div_mte.tdf" 44 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_kec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_kec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_kec " "Info: Found entity 1: add_sub_kec" {  } { { "db/add_sub_kec.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_kec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_bdc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_bdc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_bdc " "Info: Found entity 1: add_sub_bdc" {  } { { "db/add_sub_bdc.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_bdc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_jec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_jec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_jec " "Info: Found entity 1: add_sub_jec" {  } { { "db/add_sub_jec.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_jec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_iac.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_iac.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_iac " "Info: Found entity 1: add_sub_iac" {  } { { "db/add_sub_iac.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_iac.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dac_test:M2\|display_data3\[3\] data_in GND " "Warning: Reduced register \"dac_test:M2\|display_data3\[3\]\" with stuck data_in port to stuck value GND" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 85 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 96 -1 0 } } { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 95 -1 0 } } { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 97 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "843 " "Info: Implemented 843 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins"