da_tlc5620.map.qmsg

用verilong hdl语言编写的数据采样程序

{ "Info" "ISGN_MEGAFN_DESCENDANT" "dac_test:M2\|lpm_mult:Mult0\|altshift:external_latency_ffs dac_test:M2\|lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf" 347 4 0 } } { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dac_test:M2\|lpm_mult:Mult0 " "Info: Instantiated megafunction \"dac_test:M2\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 8 " "Info: Parameter \"LPM_WIDTHA\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 12 " "Info: Parameter \"LPM_WIDTHB\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Info: Parameter \"LPM_WIDTHP\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Info: Parameter \"LPM_WIDTHR\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Info: Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Info: Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Info: Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Info: Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEDICATED_MULTIPLIER_CIRCUITRY AUTO " "Info: Parameter \"DEDICATED_MULTIPLIER_CIRCUITRY\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf" 116 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dac_test:M2\|lpm_divide:Mod0 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_divide:Mod0\"" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 95 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_tul.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_tul.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_tul " "Info: Found entity 1: lpm_divide_tul" {  } { { "db/lpm_divide_tul.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/lpm_divide_tul.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_mlh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_mlh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_mlh " "Info: Found entity 1: sign_div_unsign_mlh" {  } { { "db/sign_div_unsign_mlh.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/sign_div_unsign_mlh.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_sqe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_sqe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_sqe " "Info: Found entity 1: alt_u_div_sqe" {  } { { "db/alt_u_div_sqe.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/alt_u_div_sqe.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_3dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_3dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_3dc " "Info: Found entity 1: add_sub_3dc" {  } { { "db/add_sub_3dc.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_3dc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_4dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_4dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_4dc " "Info: Found entity 1: add_sub_4dc" {  } { { "db/add_sub_4dc.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_4dc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_7dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_7dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_7dc " "Info: Found entity 1: add_sub_7dc" {  } { { "db/add_sub_7dc.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_7dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_5dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_5dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_5dc " "Info: Found entity 1: add_sub_5dc" {  } { { "db/add_sub_5dc.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_5dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_6dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_6dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_6dc " "Info: Found entity 1: add_sub_6dc" {  } { { "db/add_sub_6dc.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_6dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_59c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_59c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_59c " "Info: Found entity 1: add_sub_59c" {  } { { "db/add_sub_59c.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/add_sub_59c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dac_test:M2\|lpm_divide:Div0 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_divide:Div0\"" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 96 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_q6m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_q6m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_q6m " "Info: Found entity 1: lpm_divide_q6m" {  } { { "db/lpm_divide_q6m.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/lpm_divide_q6m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dac_test:M2\|lpm_divide:Div1 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_divide:Div1\"" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 97 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_t6m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_t6m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_t6m " "Info: Found entity 1: lpm_divide_t6m" {  } { { "db/lpm_divide_t6m.tdf" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/db/lpm_divide_t6m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}