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📄 da_tlc5620.map.qmsg

📁 用verilong hdl语言编写的数据采样程序
💻 QMSG
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dac_test:M2\|lpm_mult:Mult0 " "Info: Instantiated megafunction \"dac_test:M2\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 8 " "Info: Parameter \"LPM_WIDTHA\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 12 " "Info: Parameter \"LPM_WIDTHB\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Info: Parameter \"LPM_WIDTHP\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Info: Parameter \"LPM_WIDTHR\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Info: Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Info: Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Info: Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Info: Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEDICATED_MULTIPLIER_CIRCUITRY AUTO " "Info: Parameter \"DEDICATED_MULTIPLIER_CIRCUITRY\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] dac_test:M2\|lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dac_test:M2\|lpm_mult:Mult0 " "Info: Instantiated megafunction \"dac_test:M2\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 8 " "Info: Parameter \"LPM_WIDTHA\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 12 " "Info: Parameter \"LPM_WIDTHB\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Info: Parameter \"LPM_WIDTHP\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Info: Parameter \"LPM_WIDTHR\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Info: Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Info: Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Info: Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Info: Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEDICATED_MULTIPLIER_CIRCUITRY AUTO " "Info: Parameter \"DEDICATED_MULTIPLIER_CIRCUITRY\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder dac_test:M2\|lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\", which is child of megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } } { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dac_test:M2\|lpm_mult:Mult0 " "Info: Instantiated megafunction \"dac_test:M2\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 8 " "Info: Parameter \"LPM_WIDTHA\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 12 " "Info: Parameter \"LPM_WIDTHB\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Info: Parameter \"LPM_WIDTHP\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Info: Parameter \"LPM_WIDTHR\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Info: Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Info: Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Info: Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Info: Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEDICATED_MULTIPLIER_CIRCUITRY AUTO " "Info: Parameter \"DEDICATED_MULTIPLIER_CIRCUITRY\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:oflow_node dac_test:M2\|lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dac_test:M2\|lpm_mult:Mult0 " "Info: Instantiated megafunction \"dac_test:M2\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 8 " "Info: Parameter \"LPM_WIDTHA\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 12 " "Info: Parameter \"LPM_WIDTHB\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Info: Parameter \"LPM_WIDTHP\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Info: Parameter \"LPM_WIDTHR\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Info: Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Info: Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Info: Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Info: Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEDICATED_MULTIPLIER_CIRCUITRY AUTO " "Info: Parameter \"DEDICATED_MULTIPLIER_CIRCUITRY\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node dac_test:M2\|lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 120 6 0 } } { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dac_test:M2\|lpm_mult:Mult0 " "Info: Instantiated megafunction \"dac_test:M2\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 8 " "Info: Parameter \"LPM_WIDTHA\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 12 " "Info: Parameter \"LPM_WIDTHB\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Info: Parameter \"LPM_WIDTHP\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Info: Parameter \"LPM_WIDTHR\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Info: Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Info: Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Info: Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Info: Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEDICATED_MULTIPLIER_CIRCUITRY AUTO " "Info: Parameter \"DEDICATED_MULTIPLIER_CIRCUITRY\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|altshift:result_ext_latency_ffs dac_test:M2\|lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 284 2 0 } } { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dac_test:M2\|lpm_mult:Mult0 " "Info: Instantiated megafunction \"dac_test:M2\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 8 " "Info: Parameter \"LPM_WIDTHA\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 12 " "Info: Parameter \"LPM_WIDTHB\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Info: Parameter \"LPM_WIDTHP\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Info: Parameter \"LPM_WIDTHR\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Info: Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Info: Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Info: Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Info: Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEDICATED_MULTIPLIER_CIRCUITRY AUTO " "Info: Parameter \"DEDICATED_MULTIPLIER_CIRCUITRY\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|altshift:carry_ext_latency_ffs dac_test:M2\|lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dac_test:M2\|lpm_mult:Mult0 " "Info: Instantiated megafunction \"dac_test:M2\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 8 " "Info: Parameter \"LPM_WIDTHA\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 12 " "Info: Parameter \"LPM_WIDTHB\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Info: Parameter \"LPM_WIDTHP\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Info: Parameter \"LPM_WIDTHR\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Info: Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Info: Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Info: Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Info: Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEDICATED_MULTIPLIER_CIRCUITRY AUTO " "Info: Parameter \"DEDICATED_MULTIPLIER_CIRCUITRY\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
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