da_tlc5620.map.qmsg

用verilong hdl语言编写的数据采样程序

{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "CH451_Display DISPLAY.v(77) " "Info (10151): Verilog HDL Declaration information at DISPLAY.v(77): \"CH451_Display\" is declared here" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 77 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "DISPLAY.v 1 1 " "Warning: Using design file DISPLAY.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 DISPLAY " "Info: Found entity 1: DISPLAY" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 53 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DISPLAY DISPLAY:M3 " "Info: Elaborating entity \"DISPLAY\" for hierarchy \"DISPLAY:M3\"" {  } { { "DA_TLC5620.v" "M3" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DA_TLC5620.v" 70 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dac_test:M2\|channel\[1\] data_in GND " "Warning: Reduced register \"dac_test:M2\|channel\[1\]\" with stuck data_in port to stuck value GND" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 60 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|DA_TLC5620\|DISPLAY:M3\|state 9 " "Info: State machine \"\|DA_TLC5620\|DISPLAY:M3\|state\" contains 9 states" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|DA_TLC5620\|DISPLAY:M3\|shift_state 7 " "Info: State machine \"\|DA_TLC5620\|DISPLAY:M3\|shift_state\" contains 7 states" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|DA_TLC5620\|DISPLAY:M3\|state " "Info: Selected Auto state machine encoding method for state machine \"\|DA_TLC5620\|DISPLAY:M3\|state\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|DA_TLC5620\|DISPLAY:M3\|state " "Info: Encoding result for state machine \"\|DA_TLC5620\|DISPLAY:M3\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "9 " "Info: Completed encoding using 9 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|state.CH451_Display_temp " "Info: Encoded state bit \"DISPLAY:M3\|state.CH451_Display_temp\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|state.CH451_Display " "Info: Encoded state bit \"DISPLAY:M3\|state.CH451_Display\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|state.CH451_Display_ready " "Info: Encoded state bit \"DISPLAY:M3\|state.CH451_Display_ready\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|state.CH451_Get_data " "Info: Encoded state bit \"DISPLAY:M3\|state.CH451_Get_data\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|state.CH451_Open_display " "Info: Encoded state bit \"DISPLAY:M3\|state.CH451_Open_display\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|state.CH451_Set_display_mode " "Info: Encoded state bit \"DISPLAY:M3\|state.CH451_Set_display_mode\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|state.CH451_Reset " "Info: Encoded state bit \"DISPLAY:M3\|state.CH451_Reset\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|state.CH451_Enable_serial_port " "Info: Encoded state bit \"DISPLAY:M3\|state.CH451_Enable_serial_port\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|state.CH451_Idle " "Info: Encoded state bit \"DISPLAY:M3\|state.CH451_Idle\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Idle 000000000 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Idle\" uses code string \"000000000\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Display 010000001 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Display\" uses code string \"010000001\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Display_ready 001000001 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Display_ready\" uses code string \"001000001\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Get_data 000100001 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Get_data\" uses code string \"000100001\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Open_display 000010001 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Open_display\" uses code string \"000010001\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Set_display_mode 000001001 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Set_display_mode\" uses code string \"000001001\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Reset 000000101 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Reset\" uses code string \"000000101\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Enable_serial_port 000000011 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Enable_serial_port\" uses code string \"000000011\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Display_temp 100000001 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|state.CH451_Display_temp\" uses code string \"100000001\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 111 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|DA_TLC5620\|DISPLAY:M3\|shift_state " "Info: Selected Auto state machine encoding method for state machine \"\|DA_TLC5620\|DISPLAY:M3\|shift_state\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|DA_TLC5620\|DISPLAY:M3\|shift_state " "Info: Encoding result for state machine \"\|DA_TLC5620\|DISPLAY:M3\|shift_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "7 " "Info: Completed encoding using 7 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|shift_state.Pull_up_ch451_load " "Info: Encoded state bit \"DISPLAY:M3\|shift_state.Pull_up_ch451_load\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|shift_state.Shift_paralell_data " "Info: Encoded state bit \"DISPLAY:M3\|shift_state.Shift_paralell_data\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|shift_state.Pull_up_ch451_dclk " "Info: Encoded state bit \"DISPLAY:M3\|shift_state.Pull_up_ch451_dclk\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|shift_state.Pull_down_ch451_dclk " "Info: Encoded state bit \"DISPLAY:M3\|shift_state.Pull_down_ch451_dclk\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|shift_state.Get_shift_out_data " "Info: Encoded state bit \"DISPLAY:M3\|shift_state.Get_shift_out_data\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|shift_state.Pull_down_ch451_load " "Info: Encoded state bit \"DISPLAY:M3\|shift_state.Pull_down_ch451_load\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "DISPLAY:M3\|shift_state.Shift12_out_idle " "Info: Encoded state bit \"DISPLAY:M3\|shift_state.Shift12_out_idle\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|shift_state.Shift12_out_idle 0000000 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|shift_state.Shift12_out_idle\" uses code string \"0000000\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|shift_state.Shift_paralell_data 0100001 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|shift_state.Shift_paralell_data\" uses code string \"0100001\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|shift_state.Pull_up_ch451_dclk 0010001 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|shift_state.Pull_up_ch451_dclk\" uses code string \"0010001\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|shift_state.Pull_down_ch451_dclk 0001001 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|shift_state.Pull_down_ch451_dclk\" uses code string \"0001001\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|shift_state.Get_shift_out_data 0000101 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|shift_state.Get_shift_out_data\" uses code string \"0000101\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|shift_state.Pull_down_ch451_load 0000011 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|shift_state.Pull_down_ch451_load\" uses code string \"0000011\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DA_TLC5620\|DISPLAY:M3\|shift_state.Pull_up_ch451_load 1000001 " "Info: State \"\|DA_TLC5620\|DISPLAY:M3\|shift_state.Pull_up_ch451_load\" uses code string \"1000001\"" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 112 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf" 281 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dac_test:M2\|lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\"" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/multcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/multcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 multcore " "Info: Found entity 1: multcore" {  } { { "multcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/multcore.tdf" 175 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core dac_test:M2\|lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\", which is child of megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf" 304 5 0 } } { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dac_test:M2\|lpm_mult:Mult0 " "Info: Instantiated megafunction \"dac_test:M2\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 8 " "Info: Parameter \"LPM_WIDTHA\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 12 " "Info: Parameter \"LPM_WIDTHB\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Info: Parameter \"LPM_WIDTHP\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Info: Parameter \"LPM_WIDTHR\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Info: Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Info: Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Info: Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Info: Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEDICATED_MULTIPLIER_CIRCUITRY AUTO " "Info: Parameter \"DEDICATED_MULTIPLIER_CIRCUITRY\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/mpar_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/mpar_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mpar_add " "Info: Found entity 1: mpar_add" {  } { { "mpar_add.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/mpar_add.tdf" 60 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder dac_test:M2\|lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"dac_test:M2\|lpm_mult:Mult0\"" {  } { { "multcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/multcore.tdf" 227 7 0 } } { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 94 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}