dac_test.v

用verilong hdl语言编写的数据采样程序

/* DAC_TLC5620测试模块
 * 按KEY1键，通道A的电压值递增;
 * 按KEY2键，通道B的电压值递增;
 * 各通道的电压值显示于数码管.
 */
module dac_test(
                clk,
                rst,
                key,
                wr_n,
                wr_data,
                display_data0,
                display_data1,
                display_data2,
                display_data3
               );
  input         clk;
  input         rst;
  input  [1:0]  key;
  output        wr_n;
  output [7:0]  display_data0;
  output [7:0]  display_data1;
  output [7:0]  display_data2;
  output [7:0]  display_data3;
  output [10:0] wr_data;
  
 reg     [7:0] display_data0;   
 reg     [7:0] display_data1; 
 reg     [7:0] display_data2; 
 reg     [7:0] display_data3;   

  reg   [31:0]  count; 
  reg   [7:0]   data_code_r;
  reg   [1:0]   channel;
  reg           CLK_DIV;
  reg   [31:0]  DCLK_DIV;
  reg   [7:0]   key0_r;
  reg   [7:0]   key1_r;
  reg   [31:0]  vo_r;

parameter CLK_FREQ = 'D50_000_000;//系统时钟50MHZ
parameter DCLK_FREQ = 'D10;//AD_CLK输出时钟10/2HZ

always @(posedge clk)
  if(DCLK_DIV < (CLK_FREQ / DCLK_FREQ))
    DCLK_DIV <= DCLK_DIV+1'b1;
  else
    begin 
      DCLK_DIV <= 0;
      CLK_DIV <= ~CLK_DIV;
    end

/*高2位为通道选择，低8位为DA数据，第9位 RNG 为1时输出0到2倍Vref，为0时输出0到Vref*/
assign wr_data = {channel,1'b1,data_code_r}; //输出不翻倍
assign wr_n = 1'b0;


/*根据按键不同，选择不同的DA通道，其值递增*/
always @(posedge CLK_DIV or negedge rst ) begin
 if(!rst)
  begin
   key0_r <= 8'h00;
   key1_r <= 8'h00;
   channel<=2'b00;
   data_code_r <= 8'h00;
  end
 else
  case(key) 
    2'b10 : begin //key1
               channel <= 2'b00;
               key0_r <= key0_r + 1'b1;
               data_code_r <= key0_r;
              end
    2'b01 : begin  //key2
               channel <= 2'b01;
               key1_r <= key1_r + 1'b1;
               data_code_r <= key1_r;
              end
    default : begin end
   endcase
end

always @(negedge rst or negedge CLK_DIV )
begin
	if(!rst)
	begin
		display_data0<=8'b00000000;
		display_data1<=8'b00000000;
		display_data2<=8'b00000000;
		display_data3<=8'b00000000;
	end
    else begin
		/*电压值Vo=Vref * (RNG+1) * CODE / 256  */
		vo_r = data_code_r * 13'd3000/9'd256;
	    display_data0<=vo_r%10;
		display_data1<=vo_r/10%10;
		display_data2<=vo_r/100%10;
		display_data3<=vo_r/1000%10;			
         end
end

endmodule