📄 dds_v.sdo

📁 基于FPGA的DDS算法的实现
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        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[27\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (7183:7183:7183) (7183:7183:7183))
        (PORT clk (2189:2189:2189) (2189:2189:2189))
        (PORT ena (2031:2031:2031) (2031:2031:2031))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[28\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (398:398:398) (398:398:398))
        (PORT datab (1535:1535:1535) (1535:1535:1535))
        (PORT cin (0:0:0) (0:0:0))
        (PORT cin0 (0:0:0) (0:0:0))
        (PORT cin1 (0:0:0) (0:0:0))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (598:598:598) (598:598:598))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[28\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (7183:7183:7183) (7183:7183:7183))
        (PORT clk (2189:2189:2189) (2189:2189:2189))
        (PORT ena (2031:2031:2031) (2031:2031:2031))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[29\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (573:573:573) (573:573:573))
        (PORT datab (1572:1572:1572) (1572:1572:1572))
        (PORT cin (0:0:0) (0:0:0))
        (PORT cin0 (0:0:0) (0:0:0))
        (PORT cin1 (0:0:0) (0:0:0))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (598:598:598) (598:598:598))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[29\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (7183:7183:7183) (7183:7183:7183))
        (PORT clk (2189:2189:2189) (2189:2189:2189))
        (PORT ena (2031:2031:2031) (2031:2031:2031))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[30\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (399:399:399) (399:399:399))
        (PORT datab (1826:1826:1826) (1826:1826:1826))
        (PORT cin (0:0:0) (0:0:0))
        (PORT cin0 (0:0:0) (0:0:0))
        (PORT cin1 (0:0:0) (0:0:0))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (598:598:598) (598:598:598))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout (524:524:524) (524:524:524))
        (IOPATH datab cout (443:443:443) (443:443:443))
        (IOPATH cin cout (98:98:98) (98:98:98))
        (IOPATH cin0 cout (130:130:130) (130:130:130))
        (IOPATH cin1 cout (118:118:118) (118:118:118))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[30\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (7183:7183:7183) (7183:7183:7183))
        (PORT clk (2189:2189:2189) (2189:2189:2189))
        (PORT ena (2031:2031:2031) (2031:2031:2031))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[31\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (389:389:389) (389:389:389))
        (PORT datad (4267:4267:4267) (4267:4267:4267))
        (PORT cin (0:0:0) (0:0:0))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH datad regin (223:223:223) (223:223:223))
        (IOPATH cin regin (578:578:578) (578:578:578))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[31\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (7183:7183:7183) (7183:7183:7183))
        (PORT clk (2189:2189:2189) (2189:2189:2189))
        (PORT ena (2031:2031:2031) (2031:2031:2031))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|extra_result_regrsa\[31\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (417:417:417) (417:417:417))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|extra_result_regrsa\[31\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datac (502:502:502) (502:502:502))
        (PORT aclr (7183:7183:7183) (7183:7183:7183))
        (PORT clk (2189:2189:2189) (2189:2189:2189))
        (PORT ena (2031:2031:2031) (2031:2031:2031))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datac (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE quadrantdly0\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (386:386:386) (386:386:386))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE quadrantdly0\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2189:2189:2189) (2189:2189:2189))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE quadrantdly1\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (835:835:835) (835:835:835))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE quadrantdly1\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datac (920:920:920) (920:920:920))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2236:2236:2236) (2236:2236:2236))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (10:10:10))
      (HOLD datac (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE quadrantdly2\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (382:382:382) (382:382:382))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE quadrantdly2\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2236:2236:2236) (2236:2236:2236))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE quadrantdly2a\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (1192:1192:1192) (1192:1192:1192))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE quadrantdly2a\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datac (1277:1277:1277) (1277:1277:1277))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2238:2238:2238) (2238:2238:2238))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (10:10:10))
      (HOLD datac (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE quadrantdly2b\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (1497:1497:1497) (1497:1497:1497))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE quadrantdly2b\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datac (1582:1582:1582) (1582:1582:1582))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2240:2240:2240) (2240:2240:2240))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (10:10:10))
      (HOLD datac (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|extra_result_regrsa\[16\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (1339:1339:1339) (1339:1339:1339))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|extra_result_regrsa\[16\]\~I.lereg)
    (DELAY
      (ABSOLUTE
上一页 1 2 3 45
💿 文件大小 1923 K
👤 上传用户 magicchange
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#FPGA #DDS #算法
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