_primary.vhd

来自「基于FPGA的DDS算法的实现」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity dds is
    port(
        clk             : in     vl_logic;
        rstn            : in     vl_logic;
        clken           : in     vl_logic;
        phi_inc_i       : in     vl_logic_vector(31 downto 0);
        fsin_o          : out    vl_logic_vector(13 downto 0);
        fcos_o          : out    vl_logic_vector(13 downto 0);
        data_ready      : out    vl_logic
    );
end dds;