dds_v.sdo

基于FPGA的DDS算法的实现

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.


// 
// Device: Altera EP1S25F780C5 Package FBGA780
// 

// 
// This SDF file should be used for ModelSim (Verilog HDL output from Quartus II) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "dds")
  (DATE "04/02/2006 22:33:46")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 4.1 Build 181 06/29/2004 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE phi_inc_i\[31\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE rstn\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1234:1234:1234) (1234:1234:1234))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE clken\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE phi_inc_i\[30\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE phi_inc_i\[25\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE phi_inc_i\[20\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE phi_inc_i\[15\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE phi_inc_i\[10\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE phi_inc_i\[5\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE phi_inc_i\[0\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (392:392:392) (392:392:392))
        (PORT datab (1470:1470:1470) (1470:1470:1470))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH dataa cout (524:524:524) (524:524:524))
        (IOPATH datab cout (443:443:443) (443:443:443))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (7189:7189:7189) (7189:7189:7189))
        (PORT clk (2194:2194:2194) (2194:2194:2194))
        (PORT ena (1985:1985:1985) (1985:1985:1985))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE phi_inc_i\[4\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE phi_inc_i\[3\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE phi_inc_i\[2\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE phi_inc_i\[1\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (548:548:548) (548:548:548))
        (PORT datab (2368:2368:2368) (2368:2368:2368))
        (PORT cin (0:0:0) (0:0:0))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (7189:7189:7189) (7189:7189:7189))
        (PORT clk (2194:2194:2194) (2194:2194:2194))
        (PORT ena (1985:1985:1985) (1985:1985:1985))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[2\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (2318:2318:2318) (2318:2318:2318))
        (PORT datab (378:378:378) (378:378:378))
        (PORT cin (0:0:0) (0:0:0))
        (PORT cin0 (0:0:0) (0:0:0))
        (PORT cin1 (0:0:0) (0:0:0))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[2\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (7189:7189:7189) (7189:7189:7189))
        (PORT clk (2194:2194:2194) (2194:2194:2194))
        (PORT ena (1985:1985:1985) (1985:1985:1985))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[3\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (390:390:390) (390:390:390))
        (PORT datab (1343:1343:1343) (1343:1343:1343))
        (PORT cin (0:0:0) (0:0:0))
        (PORT cin0 (0:0:0) (0:0:0))
        (PORT cin1 (0:0:0) (0:0:0))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[3\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (7189:7189:7189) (7189:7189:7189))
        (PORT clk (2194:2194:2194) (2194:2194:2194))
        (PORT ena (1985:1985:1985) (1985:1985:1985))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[4\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (2081:2081:2081) (2081:2081:2081))
        (PORT datab (521:521:521) (521:521:521))
        (PORT cin (0:0:0) (0:0:0))
        (PORT cin0 (0:0:0) (0:0:0))
        (PORT cin1 (0:0:0) (0:0:0))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[4\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (7189:7189:7189) (7189:7189:7189))
        (PORT clk (2194:2194:2194) (2194:2194:2194))
        (PORT ena (1985:1985:1985) (1985:1985:1985))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE acc0\|altaccumulate_component\|accum_cell\|acc_cella\[5\]\~I.lecomb)