lcd_top.msg

基于FPGA的LCD1602驱动

@TM:1188210254
@W: BN153 :"":0:0:0:-1|View "prim", Cell "NGMUX", Port "CLK0": remove clock marking
@W: BN153 :"":0:0:0:-1|View "prim", Cell "NGMUX", Port "CLK1": remove clock marking
@W: BN154 :"":0:0:0:-1|View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed
@TM:1188895214
@N: BN225 :"":0:0:0:-1|Writing default property annotation file C:\Actelprj\yan\LCD_1602\synthesis\LCD_Top.map.
@TM:1188210254
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
@N: MF258 :"":0:0:0:-1|Gated clock conversion disabled 
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@TM:1188895208
@N: CG364 :"c:\actelprj\yan\lcd_1602\hdl\clock_gen.v":5:7:5:15|Synthesizing module Clock_Gen
@W: CS148 :"c:\actelprj\yan\lcd_1602\hdl\clock_gen.v":15:12:15:13|M
@N: CG179 :"c:\actelprj\yan\lcd_1602\hdl\clock_gen.v":35:27:35:33|M
@N: MF238 :"c:\actelprj\yan\lcd_1602\hdl\clock_gen.v":36:25:36:37|M
@N: CG364 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":7:7:7:16|Synthesizing module LCD_Driver
@W: BN132 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|M
@W: CL112 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|M
@W: CL171 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|M
@W: CL171 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|M
@W: CL171 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|M
@W: CL171 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|M
@W: CL171 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|M
@W: CL189 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|M
@W: CL189 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|M
@W: CL189 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|M
@W: CL189 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|M
@W: CL189 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|M
@N: CL201 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|M
@N: CG364 :"c:\actelprj\yan\lcd_1602\hdl\lcd_top.v":5:7:5:13|Synthesizing module LCD_Top
@N: CG364 :"c:\actelprj\yan\lcd_1602\smartgen\pll_1m\pll_1m.v":5:7:5:12|Synthesizing module PLL_1M
@N: CG364 :"d:\libero\synplify\synplify_862h\lib\proasic\fusion.v":260:7:260:12|Synthesizing module PLLINT
@N: CG364 :"d:\libero\synplify\synplify_862h\lib\proasic\fusion.v":1224:7:1224:9|Synthesizing module GND
@N: CG364 :"d:\libero\synplify\synplify_862h\lib\proasic\fusion.v":2043:7:2043:9|Synthesizing module VCC
@N: CG364 :"d:\libero\synplify\synplify_862h\lib\proasic\fusion.v":2974:7:2974:9|Synthesizing module PLL