📄 lcd_top.srr
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Starting Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 45MB peak: 46MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 45MB peak: 46MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 45MB peak: 46MB)
Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 46MB peak: 47MB)
High Fanout Net Report
**********************
Driver Instance / Pin Name Fanout, notes
------------------------------------------------------------------------------
U2.state[4] / Q 97
U2.state[5] / Q 93
U2.state[6] / Q 13
U2.un1_Data_Second_Buf_2_sqmuxa_0_a2[0] / Y 93
U2.un1_Data_First_Buf_1_sqmuxa_0_a2 / Y 98
rst_pad / Y 35 : 33 asynchronous set/reset
==============================================================================
Promoting Net clk_LCD on CLKINT U1.clk_BUF_inferred_clock
Promoting Net U2.un1_Data_First_Buf_1_sqmuxa on CLKINT I_1
Promoting Net U2.state[4] on CLKINT I_2
Promoting Net U2.state[5] on CLKINT I_3
Promoting Net U2.un1_Data_Second_Buf_2_sqmuxa[0] on CLKINT I_4
Buffering rst_c, fanout 35 segments 3
Replicating U2.state[6], fanout 13 segments 2
Buffering rst_c, fanout 14 segments 2
Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 45MB peak: 47MB)
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 45MB peak: 47MB)
Added 3 Buffers
Added 1 Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 45MB peak: 47MB)
Writing Analyst data base C:\Actelprj\yan\LCD_1602\synthesis\LCD_Top.srm
@N: BN225 |Writing default property annotation file C:\Actelprj\yan\LCD_1602\synthesis\LCD_Top.map.
Writing EDIF Netlist and constraint files
Found clock Clock_Gen|U1.clk_counter_inferred_clock with period 10.00ns
Found clock Clock_Gen|clk_BUF_inferred_clock with period 10.00ns
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Sep 04 16:40:24 2007
#
Top view: LCD_Top
Library name: fusion
Operating conditions: COMWC-2 ( T = 70.0, V = 1.58, P = 1.15, tree_type = balanced_tree )
Requested Frequency: 100.0 MHz
Wire load mode: top
Wire load model: fusion
Paths requested: 5
Constraint File(s):
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..
Performance Summary
*******************
Worst slack in design: -0.336
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------------------------------------
Clock_Gen|U1.clk_counter_inferred_clock 100.0 MHz 161.9 MHz 10.000 6.177 3.823 inferred Inferred_clkgroup_1
Clock_Gen|clk_BUF_inferred_clock 100.0 MHz 96.8 MHz 10.000 10.336 -0.336 inferred Inferred_clkgroup_0
===============================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Clock_Gen|clk_BUF_inferred_clock Clock_Gen|clk_BUF_inferred_clock | 10.000 -0.336 | No paths - | No paths - | No paths -
Clock_Gen|U1.clk_counter_inferred_clock Clock_Gen|U1.clk_counter_inferred_clock | 10.000 3.823 | No paths - | No paths - | No paths -
=========================================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: Clock_Gen|U1.clk_counter_inferred_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------
U1.count[1] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[1] 0.476 3.823
U1.count[0] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[0] 0.476 3.903
U1.count[2] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[2] 0.476 3.995
U1.count[3] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[3] 0.476 4.194
U1.count[4] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[4] 0.476 4.258
U1.count[5] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[5] 0.476 4.430
U1.count[6] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[6] 0.476 4.699
U1.count[7] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[7] 0.476 4.806
U1.count[8] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[8] 0.382 5.151
U1.count[9] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[9] 0.382 5.350
=============================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------
U1.count[9] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_5[9] 9.590 3.823
U1.count[5] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_5[5] 9.590 4.558
U1.count[6] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_5[6] 9.590 4.558
U1.count[7] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_5[7] 9.590 4.558
U1.count[8] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_5[8] 9.590 4.558
U1.count[0] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_5[0] 9.590 4.636
U1.count[3] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_5[3] 9.590 4.636
U1.count[4] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D I_20 9.590 5.145
U1.clk_BUF Clock_Gen|U1.clk_counter_inferred_clock DFN1E0C1 E clk_BUF6 9.670 5.356
U1.count[2] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D I_9 9.590 6.775
==================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 5.767
= Slack (non-critical) : 3.823
Number of logic level(s): 5
Starting point: U1.count[1] / Q
Ending point: U1.count[9] / D
The start point is clocked by Clock_Gen|U1.clk_counter_inferred_clock [rising] on pin CLK
The end point is clocked by Clock_Gen|U1.clk_counter_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------
U1.count[1] DFN1C1 Q Out 0.476 0.476 -
count[1] Net - - 1.017 - 5
U1.un6_count_1.I_16 AND3 B In - 1.493 -
U1.un6_count_1.I_16 AND3 Y Out 0.469 1.962 -
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