regkeys

verilog code for 3 bit sequence detector

prop_270_val
"true"
s
prop_271_name
PROP_SynthLogicalShifterExtract
s
prop_271_val
"true"
s
prop_272_name
PROP_xilxSynthRegBalancing
s
prop_272_val
"No"
s
prop_273_name
PROP_xstPackIORegister
s
prop_273_val
"Auto"
s
prop_274_name
PROP_xstSlicePacking
s
prop_274_val
"true"
s
prop_275_name
PROP_xstTristate2Logic
s
prop_275_val
"Yes"
s
prop_276_name
PROP_xstOptimizeInsPrimtives
s
prop_276_val
"false"
s
prop_277_name
PROP_xilxSynthRegDuplication
s
prop_277_val
"true"
s
prop_278_name
PROP_xstUseClockEnable
s
prop_278_val
"Yes"
s
prop_279_name
PROP_xstUseSyncSet
s
prop_279_val
"Yes"
s
prop_27_name
PROP_SimUserCompileList_launchMSim
s
prop_27_val
""
s
prop_280_name
PROP_xstUseSyncReset
s
prop_280_val
"Yes"
s
prop_281_name
PROP_VirtexSynthAutoConstrain
s
prop_281_val
"true"
s
prop_282_name
PROP_ibiswriterGeneratePackageParasitics
s
prop_282_val
"false"
s
prop_283_name
PROP_xilxMapTimingDrivenPacking
s
prop_283_val
"false"
s
prop_284_name
PROP_EnableWYSIWYG
s
prop_284_val
"None"
s
prop_285_name
PROP_xcpldUseLocConst
s
prop_285_val
"Always"
s
prop_286_name
PROP_xcpldFitDesInit
s
prop_286_val
"Low"
s
prop_287_name
PROP_xcpldFitDesTimingCst
s
prop_287_val
"true"
s
prop_288_name
PROP_CPLDFitkeepio
s
prop_288_val
"false"
s
prop_289_name
PROP_cpldBestFit
s
prop_289_val
"false"
s
prop_28_name
PROP_SimUseCustom_behav
s
prop_28_val
"false"
s
prop_290_name
PROP_xcpldFitDesMultiLogicOpt
s
prop_290_val
"true"
s
prop_291_name
PROP_cpldfit_otherCmdLineOptions
s
prop_291_val
""
s
prop_292_name
PROP_fitGenSimModel
s
prop_292_val
"false"
s
prop_293_name
PROP_cpldfitHDLeqStyle
s
prop_293_val
"Source"
s
prop_294_name
PROP_xcpldFitDesSlew
s
prop_294_val
"Fast"
s
prop_295_name
PROP_xcpldUseGlobalClocks
s
prop_295_val
"true"
s
prop_296_name
PROP_xcpldUseGlobalOutputEnables
s
prop_296_val
"true"
s
prop_297_name
PROP_xcpldUseGlobalSetReset
s
prop_297_val
"true"
s
prop_298_name
PROP_hprep6_autosig
s
prop_298_val
"false"
s
prop_299_name
PROP_hprep6_otherCmdLineOptions
s
prop_299_val
""
s
prop_29_name
PROP_SimDo
s
prop_29_val
"true"
s
prop_2_name
PROP_StartImpView
s
prop_2_val
""
s
prop_300_name
PROP_xcpldFittimRptOption
s
prop_300_val
"Summary"
s
prop_301_name
PROP_taengine_otherCmdLineOptions
s
prop_301_val
""
s
prop_302_name
PROP_xilxSynthMacroPreserve
s
prop_302_val
"true"
s
prop_303_name
PROP_xilxSynthXORPreserve
s
prop_303_val
"true"
s
prop_304_name
PROP_xilxSynthKeepHierarchy_CPLD
s
prop_304_val
"Yes"
s
prop_305_name
PROP_PlsClockEnable
s
prop_305_val
"true"
s
prop_306_name
PROP_CompxlibAbelLib
s
prop_306_val
"true"
s
prop_307_name
PROP_CompxlibCPLDDetLib
s
prop_307_val
"true"
s
prop_308_name
PROP_xcpldFitTemplate_xpla3
s
prop_308_val
"Optimize Density"
s
prop_309_name
PROP_FunctionBlockInputLimit
s
prop_309_val
"38"
s
prop_30_name
PROP_SimUseCustom_postXlate
s
prop_30_val
"false"
s
prop_310_name
PROP_xcpldFitDesInputLmt_xbr
s
prop_310_val
"32"
s
prop_311_name
PROP_xcpldFitDesUnused
s
prop_311_val
"Keeper"
s
prop_312_name
PROP_xcpldFitDesTriMode
s
prop_312_val
"Keeper"
s
prop_313_name
PROP_xcpldFitDesVolt
s
prop_313_val
"LVCMOS18"
s
prop_314_name
PROP_UseDataGate
s
prop_314_val
"true"
s
prop_315_name
PROP_xilxBitgCfg_GenOpt_IEEE1532File_xbr
s
prop_315_val
"false"
s
prop_316_name
PROP_usedsp48
s
prop_316_val
"Auto"
s
prop_317_name
PROP_xstDSPUtilRatio
s
prop_317_val
"100"
s
prop_318_name
PROPEXT_xilxSynthAddBufg_spartan3
s
prop_318_val
"8"
s
prop_319_name
PROPEXT_xilxBitgCfg_Rate_spartan3
s
prop_319_val
"Default (6)"
s
prop_31_name
PROP_SimUseCustom_postMap
s
prop_31_val
"false"
s
prop_320_name
PROPEXT_xilxBitgCfg_DCIUpdateMode_spartan3
s
prop_320_val
"As Required"
s
prop_321_name
PROP_xilxBitgCfg_GenOpt_IEEE1532File
s
prop_321_val
"false"
s
prop_322_name
PROP_xilxBitgCfg_GenOpt_EnableCRC
s
prop_322_val
"true"
s
prop_323_name
PROP_xilxBitgCfg_PwrDown
s
prop_323_val
"Pull Up"
s
prop_324_name
PROP_xilxBitgCfg_DCMShutdown
s
prop_324_val
"false"
s
prop_325_name
PROP_xilxBitgCfg_DCMBandgap
s
prop_325_val
"false"
s
prop_326_name
PROP_xilxBitgStart_Clk_MatchCycle
s
prop_326_val
"Auto"
s
prop_327_name
PROP_bitgen_Encrypt_keySeq0
s
prop_327_val
"None"
s
prop_328_name
PROP_bitgen_Encrypt_keySeq1
s
prop_328_val
"None"
s
prop_329_name
PROP_bitgen_Encrypt_keySeq2
s
prop_329_val
"None"
s
prop_32_name
PROP_SimUseCustom_postPar
s
prop_32_val
"false"
s
prop_330_name
PROP_bitgen_Encrypt_keySeq3
s
prop_330_val
"None"
s
prop_331_name
PROP_bitgen_Encrypt_keySeq4
s
prop_331_val
"None"
s
prop_332_name
PROP_bitgen_Encrypt_keySeq5
s
prop_332_val
"None"
s
prop_333_name
PROP_bitgen_Encrypt_startKey
s
prop_333_val
"None"
s
prop_334_name
PROP_bitgen_Encrypt_startCBC
s
prop_334_val
""
s
prop_335_name
PROPEXT_xilxMapGenInputK_virtex2
s
prop_335_val
"4"
s
prop_336_name
PROPEXT_SynthMultStyle_virtex2
s
prop_336_val
"Auto"
s
prop_337_name
PROPEXT_xilxSynthMaxFanout_virtex2
s
prop_337_val
"500"
s
prop_338_name
PROP_TopDesignUnit
s
prop_338_val
""
s
prop_339_name
PROP_TopDesignUnit
s
prop_339_val
""
s
prop_33_name
PROP_ModelSimUseConfigName
s
prop_33_val
"false"
s
prop_340_name
PROP_TopDesignUnit
s
prop_340_val
""
s
prop_341_name
PROP_TopDesignUnit
s
prop_341_val
""
s
prop_342_name
PROP_TopDesignUnit
s
prop_342_val
""
s
prop_343_name
PROP_TopDesignUnit
s
prop_343_val
""
s
prop_344_name
PROP_TopDesignUnit
s
prop_344_val
""
s
prop_345_name
PROP_TopDesignUnit
s
prop_345_val
""
s
prop_346_name
PROP_TopDesignUnit
s
prop_346_val
""
s
prop_347_name
PROP_TopDesignUnit
s
prop_347_val
""
s
prop_348_name
PROP_TopDesignUnit
s
prop_348_val
""
s
prop_349_name
PROP_TopDesignUnit
s
prop_349_val
""
s
prop_34_name
PROP_MSimSDFTimingToBeRead
s
prop_34_val
"Setup Time"
s
prop_350_name
PROP_TopDesignUnit
s
prop_350_val
""
s
prop_351_name
PROP_TopDesignUnit
s
prop_351_val
""
s
prop_352_name
PROP_TopDesignUnit
s
prop_352_val
""
s
prop_353_name
PROP_TopDesignUnit
s
prop_353_val
""
s
prop_354_name
PROP_TopDesignUnit
s
prop_354_val
""
s
prop_355_name
PROP_ISimIncreCompilation
s
prop_355_val
"true"
s
prop_356_name
PROP_ISimIncreCompilation
s
prop_356_val
"true"
s
prop_357_name
PROP_ISimIncreCompilation
s
prop_357_val
"true"
s
prop_358_name
PROP_ISimIncreCompilation
s
prop_358_val
"true"
s
prop_359_name
PROP_ISimIncreCompilation
s
prop_359_val
"true"
s
prop_35_name
PROP_OverwriteSym
s
prop_35_val
"false"
s
prop_360_name
PROP_ISimCompileForHdlDebug
s
prop_360_val
"true"
s
prop_361_name
PROP_ISimCompileForHdlDebug
s
prop_361_val
"true"
s
prop_362_name
PROP_ISimCompileForHdlDebug
s
prop_362_val
"true"
s
prop_363_name
PROP_ISimCompileForHdlDebug
s
prop_363_val
"true"
s
prop_364_name
PROP_ISimValueRangeCheck
s
prop_364_val
"false"
s
prop_365_name
PROP_ISimValueRangeCheck
s
prop_365_val
"false"
s
prop_366_name
PROP_ISimValueRangeCheck
s
prop_366_val
"false"
s
prop_367_name
PROP_ISimValueRangeCheck
s
prop_367_val
"false"
s
prop_368_name
PROP_ISimValueRangeCheck
s
prop_368_val
"false"
s
prop_369_name
PROP_ISimSpecifySearchDirectory
s
prop_369_val
""
s
prop_36_name
PROP_CompxlibOutputDir
s
prop_36_val
"$XILINX/<language>/<simulator>"
s
prop_370_name
PROP_ISimSpecifySearchDirectory
s
prop_370_val
""
s
prop_371_name
PROP_ISimSpecifySearchDirectory
s
prop_371_val
""
s
prop_372_name
PROP_ISimSpecifySearchDirectory
s
prop_372_val
""
s
prop_373_name
PROP_ISimSpecifySearchDirectory
s
prop_373_val
""
s
prop_374_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_374_val
""
s
prop_375_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_375_val
""
s
prop_376_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_376_val
""
s
prop_377_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_377_val
""
s
prop_378_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_378_val
""
s
prop_379_name
PROP_xstVeriIncludeDir
s
prop_379_val
""
s
prop_37_name
PROP_CompxlibOverwriteLib
s
prop_37_val
"Overwrite"
s
prop_380_name
PROP_xstVeriIncludeDir
s
prop_380_val
""
s
prop_381_name
PROP_ISimSpecifySearchDir
s
prop_381_val
""
s
prop_382_name
PROP_DevFamily
s
prop_382_val
"Spartan3"
s
prop_383_name
PROP_Simulator
s
prop_383_val
"ISE Simulator (VHDL/Verilog)"
s
prop_384_name
PROP_SmartGuideFileName
s
prop_384_val
"seqdet_guide.ncd"
s
prop_385_name
PROP_vsim_otherCmdLineOptions
s
prop_385_val
""
s
prop_386_name
PROP_vlog_otherCmdLineOptions
s
prop_386_val
""
s
prop_387_name
PROP_vcom_otherCmdLineOptions
s
prop_387_val
""
s
prop_388_name
PROP_ModelSimSignalWin
s
prop_388_val
"true"
s
prop_389_name
PROP_ModelSimWaveWin
s
prop_389_val
"true"
s
prop_38_name
PROP_CompxlibOtherCompxlibOpts
s
prop_38_val
""
s
prop_390_name
PROP_ModelSimStructWin
s
prop_390_val
"true"
s
prop_391_name
PROP_ModelSimSourceWin
s
prop_391_val
"false"
s
prop_392_name
PROP_ModelSimListWin
s
prop_392_val
"false"
s
prop_393_name
PROP_ModelSimVarsWin
s
prop_393_val
"false"
s
prop_394_name
PROP_ModelSimProcWin
s
prop_394_val
"false"
s
prop_395_name
PROP_ModelSimDataWin
s
prop_395_val
"false"
s
prop_396_name
PROP_ModelSimSimRes
s
prop_396_val
"Default (1 ps)"
s
prop_397_name
PROP_SimSyntax
s
prop_397_val
"93"
s
prop_398_name
PROP_SimUseExpDeclOnly
s
prop_398_val
"true"
s
prop_399_name
PROP_ModelSimSimRunTime_tb
s
prop_399_val
"1000ns"
s
prop_39_name
PROP_CompxlibSimPrimatives
s
prop_39_val
"true"
s
prop_3_name
PROP_StopImpView
s
prop_3_val
"AbstractSynthesis"
s
prop_400_name
PROP_ModelSimUutInstName_postMap
s
prop_400_val
"UUT"
s
prop_401_name
PROP_ModelSimUutInstName_postPar
s
prop_401_val
"UUT"
s
prop_402_name
PROP_ModelSimUutInstName_postFit
s
prop_402_val
"UUT"
s
prop_403_name
PROP_SimGenVcdFile
s
prop_403_val
"false"
s
prop_404_name
PROP_SimCustom_launchMSim
s
prop_404_val
""
s
prop_405_name
PROP_SimCustom_behav
s
prop_405_val
""
s
prop_406_name
PROP_SimUserCompileList_behav
s
prop_406_val
""
s
prop_407_name
PROP_SimCustom_postXlate
s
prop_407_val
""
s
prop_408_name
PROP_SimCustom_postMap
s
prop_408_val
""
s
prop_409_name
PROP_SimCustom_postPar
s
prop_409_val
""
s
prop_40_name
PROP_XPORTInpFileName
s
prop_40_val
""
s
prop_410_name
PROP_ModelSimSimRunTime_tbw
s
prop_410_val
"1000ns"
s
prop_411_name
PROP_ModelSimConfigName
s
prop_411_val
"Default"
s
prop_412_name
PROP_SimModelRenTopLevInstTo
s
prop_412_val
"UUT"
s
prop_413_name
PROP_SynthConstraintsFile
s
prop_413_val
""
s
prop_414_name
PROP_ISimCustomSimCmdFileName_par_tb
s
prop_414_val
""
s
prop_415_name
PROP_ISimCustomSimCmdFileName_par_tbw
s
prop_415_val
""
s
prop_416_name
PROP_ISimCustomSimCmdFileName_behav_tb
s
prop_416_val
""
s
prop_417_name
PROP_ISimCustomSimCmdFileName_behav_tbw
s
prop_417_val
""
s
prop_418_name
PROP_ISimCustomSimCmdFileName_gen_tbw
s
prop_418_val
""
s
prop_419_name
PROP_ISimCustomSimCmdFileName_launch
s
prop_419_val
""
s
prop_41_name
PROP_XPORTInpFileType
s
prop_41_val
"ABEL"
s
prop_420_name
PROP_ISimSimulationRun_par_tb
s
prop_420_val
"true"
s
prop_421_name
PROP_ISimSimulationRun_par_tbw
s
prop_421_val
"true"
s
prop_422_name
PROP_ISimSimulationRun_behav_tb
s
prop_422_val
"true"
s
prop_423_name
PROP_ISimSimulationRun_behav_tbw
s
prop_423_val
"true"
s
prop_424_name
PROP_ISimStoreAllSignalTransitions_par_tb
s
prop_424_val
"false"
s
prop_425_name
PROP_ISimStoreAllSignalTransitions_par_tbw
s
prop_425_val
"false"
s
prop_426_name
PROP_ISimStoreAllSignalTransitions_behav_tb
s
prop_426_val
"false"
s
prop_427_name
PROP_ISimStoreAllSignalTransitions_behav_tbw
s
prop_427_val
"false"
s
prop_428_name
PROP_ISimGenVCDFile_par_tb
s
prop_428_val
"false"
s
prop_429_name
PROP_ISimGenVCDFile_par_tbw
s
prop_429_val
"false"
s
prop_42_name
PROP_XPORTOutFileType
s
prop_42_val
"VHDL"
s
prop_430_name
PROP_ISimCustomCompilationOrderFile
s
prop_430_val
""
s
prop_431_name
PROP_impactBaud
s
prop_431_val
"None"
s
prop_432_name
PROP_impactConfigMode
s
prop_432_val
"None"
s
prop_433_name
PROP_impactPort
s
prop_433_val
"Auto - default"
s
prop_434_name
PROP_XPowerOptAdvancedVerboseRpt
s
prop_434_val
"false"
s
prop_435_name
PROP_XPowerOptMaxNumberLines
s
prop_435_val
"1000"
s
prop_436_name
PROP_xstSafeImplement
s
prop_436_val
"No"
s
prop_437_name
PROP_XplorerRunType
s
prop_437_val
"Yes"
s
prop_438_name
PROP_XplorerNumIterations
s
prop_438_val
"7"
s
prop_439_name
PROP_XplorerEnableRetiming
s
prop_439_val
"true"
s
prop_43_name
PROP_XPORTlistInpFiles
s
prop_43_val
"false"
s
prop_440_name
PROP_XplorerWarnToBackup
s