tb_pif2wb.vhd

This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test_bridge IS
END test_bridge;

ARCHITECTURE testbench_arch OF test_bridge IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

    COMPONENT top
        PORT (
            SCLK : In std_logic;
            CLKETH : In std_logic;
            SReset : In std_logic;
            PIReqVALID : In std_logic;
            PIReqCNTL : In std_logic_vector (7 DownTo 0);
            PIReqADRS : In std_logic_vector (31 DownTo 0);
            PIReqDATA : In std_logic_vector (31 DownTo 0);
            PIReqDataBE : In std_logic_vector (3 DownTo 0);
            PIRespRDY : In std_logic;
            probe_mtxd_pad_o : Out std_logic_vector (3 DownTo 0);
            probe_mtxen_pad_o : Out std_logic;
            mtxerr_pad_o : Out std_logic;
            probe_mrxd_pad_i : In std_logic_vector (3 DownTo 0);
            probe_mrxdv_pad_i : In std_logic;
            probe_mrxerr_pad_i : In std_logic;
            probe_mcoll_pad_i : In std_logic;
            probe_mcrs_pad_i : In std_logic;
            probe_mdc_pad_o : Out std_logic;
            probe_md_pad_i : In std_logic;
            probe_md_pad_o : Out std_logic;
            probe_md_padoe_o : Out std_logic;
            interrupt : Out std_logic
        );
    END COMPONENT;

    SIGNAL SCLK : std_logic := '0';
    SIGNAL CLKETH : std_logic := '0';
    SIGNAL SReset : std_logic := '0';
    SIGNAL PIReqVALID : std_logic := '0';
    SIGNAL PIReqCNTL : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL PIReqADRS : std_logic_vector (31 DownTo 0) := "00000000000000000000000000000000";
    SIGNAL PIReqDATA : std_logic_vector (31 DownTo 0) := "00000000000000000000000000000000";
    SIGNAL PIReqDataBE : std_logic_vector (3 DownTo 0) := "0000";
    SIGNAL PIRespRDY : std_logic := '0';
    SIGNAL probe_mtxd_pad_o : std_logic_vector (3 DownTo 0) := "0000";
    SIGNAL probe_mtxen_pad_o : std_logic := '0';
    SIGNAL mtxerr_pad_o : std_logic := '0';
    SIGNAL probe_mrxd_pad_i : std_logic_vector (3 DownTo 0) := "0000";
    SIGNAL probe_mrxdv_pad_i : std_logic := '0';
    SIGNAL probe_mrxerr_pad_i : std_logic := '0';
    SIGNAL probe_mcoll_pad_i : std_logic := '0';
    SIGNAL probe_mcrs_pad_i : std_logic := '0';
    SIGNAL probe_mdc_pad_o : std_logic := '0';
    SIGNAL probe_md_pad_i : std_logic := '0';
    SIGNAL probe_md_pad_o : std_logic := '0';
    SIGNAL probe_md_padoe_o : std_logic := '0';
    SIGNAL interrupt : std_logic := '0';

    constant PERIOD_CLKETH : time := 40 ns;
    constant DUTY_CYCLE_CLKETH : real := 0.5;
    constant OFFSET_CLKETH : time := 100 ns;
    constant PERIOD_SCLK : time := 20 ns;
    constant DUTY_CYCLE_SCLK : real := 0.5;
    constant OFFSET_SCLK : time := 100 ns;

    BEGIN
        UUT : top
        PORT MAP (
            SCLK => SCLK,
            CLKETH => CLKETH,
            SReset => SReset,
            PIReqVALID => PIReqVALID,
            PIReqCNTL => PIReqCNTL,
            PIReqADRS => PIReqADRS,
            PIReqDATA => PIReqDATA,
            PIReqDataBE => PIReqDataBE,
            PIRespRDY => PIRespRDY,
            probe_mtxd_pad_o => probe_mtxd_pad_o,
            probe_mtxen_pad_o => probe_mtxen_pad_o,
            mtxerr_pad_o => mtxerr_pad_o,
            probe_mrxd_pad_i => probe_mrxd_pad_i,
            probe_mrxdv_pad_i => probe_mrxdv_pad_i,
            probe_mrxerr_pad_i => probe_mrxerr_pad_i,
            probe_mcoll_pad_i => probe_mcoll_pad_i,
            probe_mcrs_pad_i => probe_mcrs_pad_i,
            probe_mdc_pad_o => probe_mdc_pad_o,
            probe_md_pad_i => probe_md_pad_i,
            probe_md_pad_o => probe_md_pad_o,
            probe_md_padoe_o => probe_md_padoe_o,
            interrupt => interrupt
        );

        PROCESS    -- clock process for CLK ETHERNET CONTROLLER
        BEGIN
            WAIT for OFFSET_CLKETH;
            CLOCK_LOOP : LOOP
                CLKETH <= '0';
                WAIT FOR (PERIOD_CLKETH - (PERIOD_CLKETH * DUTY_CYCLE_CLKETH));
                CLKETH <= '1';
                WAIT FOR (PERIOD_CLKETH * DUTY_CYCLE_CLKETH);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS    -- clock process for SCLK
        BEGIN
            WAIT for OFFSET_SCLK;
            CLOCK_LOOP : LOOP
                SCLK <= '0';
                WAIT FOR (PERIOD_SCLK - (PERIOD_SCLK * DUTY_CYCLE_SCLK));
                SCLK <= '1';
                WAIT FOR (PERIOD_SCLK * DUTY_CYCLE_SCLK);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS    -- Process for CLKETH
            BEGIN
                WAIT FOR 2040 ns;

            END PROCESS;

            PROCESS    -- Process for SCLK
                BEGIN
                    -- -------------  Current Time:  95ns Reset the System
                    WAIT FOR 95 ns;
                    SReset <= '1';
                    PIRespRDY <= '1';
                    -- ------------------------------------- End reset
                    -- -------------  Current Time:  135ns
                    WAIT FOR 40 ns;
                    SReset <= '0';
                    -- ------------------------------------- Single Read at Address 0x60000194
                    -- -------------  Current Time:  175ns   Test address out of range
                    WAIT FOR 40 ns;
                    PIReqVALID <= '1';
                    PIReqCNTL <= "00000001";
                    PIReqADRS <= "01100000000000000000100100010000";
                    PIReqDATA <= "10000000000000000000000000000000";
                    PIReqDataBE <= "1111";
                    -- ------------------------------------- End of Single Read
                    -- -------------  Current Time:  195ns
                    WAIT FOR 20 ns;
                    PIReqVALID <= '0';
                    PIReqCNTL <= "11111111";
                    PIReqDataBE <= "0000";
                    -- ------------------------------------- Single Read at Address 0x80000000
                    -- -------------  Current Time:  235ns   First Ethernet register	
                    WAIT FOR 40 ns;
                    PIReqVALID <= '1';
                    PIReqCNTL <= "00000001";
                    PIReqADRS <= "10000000000000000000000000000000";
                    PIReqDataBE <= "1111";
                    -- ------------------------------------- End of Single Read
                    -- -------------  Current Time:  255ns
                    WAIT FOR 20 ns;
                    PIReqVALID <= '0';
                    PIReqCNTL <= "11111111";
                    PIReqDataBE <= "0000";
                    -- ------------------------------------- Single Write at Address 0x80000000
                    -- -------------  Current Time:  295ns
                    WAIT FOR 40 ns;
                    PIReqVALID <= '1';
                    PIReqCNTL <= "10000001";
                    PIReqDATA <= "00000000000000001111111111111111";
                    PIReqDataBE <= "1111";
                    -- ------------------------------------- End of Single Write
                    -- -------------  Current Time:  315ns
                    WAIT FOR 20 ns;
                    PIReqVALID <= '0';
                    PIReqCNTL <= "11111111";
                    PIReqDataBE <= "0000";
                    -- ------------------------------------- Single Read at Address 0x80000000
                    -- -------------  Current Time:  355ns
                    WAIT FOR 40 ns;
                    PIReqVALID <= '1';
                    PIReqCNTL <= "00000001";
                    PIReqDATA <= "10000000000000000000000000000000";
                    PIReqDataBE <= "1111";
                    -- ------------------------------------- End of Single Read
                    -- -------------  Current Time:  375ns