📄 register3.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity register3 is
Port (clk, reset: in std_logic;
cop: in std_logic_vector (1 downto 0);
indata: in std_logic_vector (7 downto 0);
outdata: out std_logic_vector (7 downto 0)
);
end register3;
architecture Behavioral of register3 is
begin
process (clk)
begin
if (clk'EVENT and clk='1') THEN
end Behavioral;
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