📄 mux5.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux5 is
Generic ( size : integer := 8 );
Port ( d0 : in std_logic_vector(size-1 downto 0);
d1 : in std_logic_vector(size-1 downto 0);
d2 : in std_logic_vector(size-1 downto 0);
d3 : in std_logic_vector(size-1 downto 0);
d4 : in std_logic_vector(size-1 downto 0);
s : in std_logic_vector(2 downto 0);
o : out std_logic_vector(size-1 downto 0));
end mux5;
architecture Behavioral of mux5 is
begin
PROCESS (s, d0, d1, d2, d3, d4)
begin
IF (s = "000") THEN o <= d0;
ELSIF (s = "001") THEN o <= d1;
ELSIF (s = "010") THEN o <= d2;
ELSIF (s = "011") THEN o <= d3;
ELSIF (s = "100") THEN o <= d4; END IF;
END PROCESS;
end Behavioral;
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