__projnav.log

vhdl code for GIF Image Viewer

    MUXCY:CI->O            1   0.044   0.000  inst_vgamem_Mcompar__n0030_inst_cy_18 (inst_vgamem_Mcompar__n0030_inst_cy_18)
    MUXCY:CI->O            1   0.044   0.000  inst_vgamem_Mcompar__n0030_inst_cy_19 (inst_vgamem_Mcompar__n0030_inst_cy_19)
    MUXCY:CI->O            1   0.044   0.000  inst_vgamem_Mcompar__n0030_inst_cy_20 (inst_vgamem_Mcompar__n0030_inst_cy_20)
    MUXCY:CI->O            1   0.044   1.035  inst_vgamem_Mcompar__n0030_inst_cy_21 (inst_vgamem_N315)
    LUT4:I0->O            40   0.573   3.780  inst_vgamem_I_curraddr_19__n0004 (inst_vgamem_N326)
    LUT4:I3->O             1   0.573   0.000  inst_memreadmux_Mmux_memaddr_inst_lut3_151 (inst_memreadmux_Mmux_memaddr_xstma
cro_int_tempname218)
    MUXF5:I1->O           18   0.134   2.700  inst_memreadmux_Mmux_memaddr_inst_mux_f5_67 (N553)
    LUT4:I1->O            11   0.573   2.070  I_inst_memreadmux_Mmux_readdata_I15_Result (N763)
    LUT4:I3->O             1   0.573   1.035  I_8_LUT_64 (N1006)
    LUT4:I0->O             1   0.573   1.035  I_inst_prgramdacver2_prgdata_0 (ramdacdata_0_OBUFT)
    OBUFT:I->O                 4.787          ramdacdata_0_OBUFT (ramdacdata_0)
    ----------------------------------------
    Total                     31.454ns (15.317ns logic, 16.137ns route)
                                       (48.7% logic, 51.3% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               23.122ns (Levels of Logic = 9)
  Source:            resetl
  Destination:       ramdacdata_0

  Data Path: resetl to ramdacdata_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O             14   0.768   2.340  resetl_IBUF (resetl_IBUF)
    LUT2:I0->O             1   0.573   1.035  inst_vgamem_I_0_LUT_9 (inst_vgamem_N324)
    LUT4:I3->O            40   0.573   3.780  inst_vgamem_I_curraddr_19__n0004 (inst_vgamem_N326)
    LUT4:I3->O             1   0.573   0.000  inst_memreadmux_Mmux_memaddr_inst_lut3_151 (inst_memreadmux_Mmux_memaddr_xstma
cro_int_tempname218)
    MUXF5:I1->O           18   0.134   2.700  inst_memreadmux_Mmux_memaddr_inst_mux_f5_67 (N553)
    LUT4:I1->O            11   0.573   2.070  I_inst_memreadmux_Mmux_readdata_I15_Result (N763)
    LUT4:I3->O             1   0.573   1.035  I_8_LUT_64 (N1006)
    LUT4:I0->O             1   0.573   1.035  I_inst_prgramdacver2_prgdata_0 (ramdacdata_0_OBUFT)
    OBUFT:I->O                 4.787          ramdacdata_0_OBUFT (ramdacdata_0)
    ----------------------------------------
    Total                     23.122ns (9.127ns logic, 13.995ns route)
                                       (39.5% logic, 60.5% route)

=========================================================================
CPU : 35.61 / 35.64 s | Elapsed : 36.00 / 36.00 s
 
--> 
EXEWRAP detected that program 'C:/Xilinx/bin/nt/xst.exe' completed successfully.

Done: completed successfully.

Starting: 'exewrap @__ednTOngd_exewrap.rsp'


Starting: 'ngdbuild -f __ngdbuild.rsp '


Release 4.1i - ngdbuild E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd e:/gif.3.21m/_ngo -nt timestamp -p xcv50-pq240-6
gif.ngc gif.ngd 

Reading NGO file "E:/GIF.3.21m/gif.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "gif.ucf" ...
WARNING:NgdBuild:383 - A case sensitive search for the INST, PAD, or NET element
   refered to by a constraint entry in the UCF file that accompanies this design
   has failed, while a case insensitive search is in progress. The result of the
   case insenstive search will be used, but warnings will accompany each and
   every use of a case insensitive result. Constraints are case sensitive with
   respect to user-specified identifiers, which includes names of logic elements
   in a design. For the sake of compatibility with currently existing .xnf,
   .xtf, and .xff files, Software will allow a case insensitive search for INST,
   PAD, or NET elements referenced in a .ucf file.
WARNING:NgdBuild:385 - Found case insensitive match for NET name 'resetL'. NET
   is 'resetl'.

Checking timing specifications ...

Checking expanded design ...
WARNING:NgdBuild:477 - clock net 'pixelclk_OBUF' has non-clock connections

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "gif.ngd" ...

Writing NGDBUILD log file "gif.bld"...

NGDBUILD done.
EXEWRAP detected that program 'ngdbuild' completed successfully.

Done: completed successfully.

Starting: 'exewrap @_ngdTOnc1_exewrap.rsp'


Creating TCL Process
Starting: 'map -f _map.rsp'


Release 4.1i - Map E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Using target part "v50pq240-6".
Removing unused or disabled logic...
Running cover...
Writing file gif.ngm...
Running directed packing...
Running delay-based packing...
Running related packing...
Writing design file "gif.ncd"...

Design Summary:
   Number of errors:      0
   Number of warnings:    4
   Number of Slices:                747 out of    768   97%
   Number of Slices containing
      unrelated logic:                0 out of    747    0%
   Total Number Slice Registers:    464 out of  1,536   30%
      Number used as Flip Flops:                  426
      Number used as Latches:                      38
   Total Number 4 input LUTs:     1,205 out of  1,536   78%
      Number used as LUTs:                      1,128
      Number used as a route-thru:                 77
   Number of bonded IOBs:            96 out of    166   57%
      IOB Flip Flops:                               3
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
Total equivalent gate count for design:  12,790
Additional JTAG gate count for IOBs:  4,656

Mapping completed.
See MAP report file "gif.mrp" for details.
Tcl C:/Xilinx/data/projnav/_map.tcl detected that program 'map -f _map.rsp' completed successfully.

Done: completed successfully.

Starting: 'exewrap @_nc1TOncd_exewrap.rsp'


Creating TCL Process
Found _prepar.rsp
Starting: 'par -f _par.rsp'


Release 4.1i - Par E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


WARNING:Par:69 - Option "-xe" overrides some effects of "-ol".


Constraints file: gif.pcf

Loading design for application par from file par_temp.ncd.
   "gif" is an NCD, version 2.36, device xcv50, package pq240, speed -6
Loading device for application par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  FINAL 1.115 2001-06-20.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            96 out of 166    57%
      Number of LOCed External IOBs   96 out of 96    100%

   Number of SLICEs                  747 out of 768    97%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)
Extra effort level (-xe):     0 (set by user)

Starting the placer. REAL time: 0 secs 
Placement pass 1 ......................................
Placer score = 142035
Placement pass 2 .................................
Placer score = 144065
Optimizing ... 
Placer score = 122505
All IOBs have been constrained to specific sites.
Placer completed in real time: 3 secs 

Dumping design to file gif.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 3 secs 

0 connection(s) routed; 4627 unrouted active, 44 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 4 secs 
Starting iterative routing. 
Routing active signals.
.......
End of iteration 1 
4671 successful; 0 unrouted; (0) REAL time: 6 secs 
Constraints are met. 
Total REAL time: 7 secs 
Total CPU  time: 6 secs 
End of route.  4671 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 7 secs 
Total CPU time to Router completion: 6 secs 

Generating PAR statistics.
Dumping design to file gif.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 8 secs 
Total CPU time to PAR completion: 7 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

PAR done.
Tcl C:/Xilinx/data/projnav/_par.tcl detected that program 'par -f _par.rsp' completed successfully.

PAR completed successfully
Done: completed successfully.

Starting: 'exewrap -tcl -command C:/Xilinx/data/projnav/_bitgen.tcl bitgen.rsp gif'


Done: completed successfully.

Starting: 'exewrap -tapkeep -tcl -command C:/Xilinx/data/projnav/_utTObit.tcl gif'


Creating TCL Process
Starting: 'bitgen -f gif.ut gif.ncd'


Release 4.1i - Bitgen E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

Loading design for application Bitgen from file gif.ncd.
   "gif" is an NCD, version 2.36, device xcv50, package pq240, speed -6
Loading device for application Bitgen from file 'v50.nph' in environment
C:/Xilinx.
Opened constraints file gif.pcf.

Tue Mar 23 00:35:00 2004

Running DRC.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net inst_vgamem_N326 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net inst_lzw_mux1_N156 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net N1186 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
DRC detected 0 errors and 3 warnings.
Creating bit map...
Saving bit stream in "gif.bit".
Bitstream generation is complete.
Tcl C:/Xilinx/data/projnav/_utTObit.tcl detected that program 'bitgen -f gif.ut gif.ncd' completed successfully.


Done: completed successfully.