__projnav.log

vhdl code for GIF Image Viewer

Register inst_lzw_seladdr2_2 equivalent to inst_lzw_opout2 has been removed
FlipFlop halfclk has been replicated 3 time(s)
FlipFlop inst_lzw_reset has been replicated 1 time(s)
FlipFlop inst_vgamem_hsyncb has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop inst_vgamem_vsyncb has been replicated 1 time(s) to handle iob=true attribute.
=========================================================================
Final Results
Top Level Output File Name         : gif
Output Format                      : NGC
Optimization Criterion             : Area
Target Technology                  : virtex
Keep Hierarchy                     : No
Macro Generator                    : macro+

Macro Statistics
# FSMs                             : 5
# Registers                        : 70
  16-bit register                  : 5
  32-bit register                  : 6
  11-bit register                  : 1
  10-bit register                  : 1
  8-bit register                   : 5
  20-bit register                  : 3
  1-bit register                   : 33
  2-bit register                   : 10
  3-bit register                   : 4
  4-bit register                   : 2
# Multiplexers                     : 6
  16-bit 5-to-1 multiplexer        : 1
  32-bit 4-to-1 multiplexer        : 2
  1-bit 4-to-1 multiplexer         : 2
  20-bit 4-to-1 multiplexer        : 1
# Tristates                        : 4
  16-bit tristate buffer           : 2
  8-bit tristate buffer            : 1
  3-bit tristate buffer            : 1
# Decoders                         : 1
  1-of-8 decoder                   : 1
# Adders/Subtractors               : 34
  9-bit adder                      : 1
  32-bit adder                     : 6
  32-bit subtractor                : 6
  10-bit subtractor                : 1
  20-bit adder                     : 3
  11-bit adder                     : 1
  10-bit adder                     : 5
  12-bit adder                     : 1
  8-bit adder                      : 5
  4-bit subtractor                 : 1
  12-bit subtractor                : 1
# Comparators                      : 26
  11-bit comparator greater        : 1
  10-bit comparator greater        : 1
  11-bit comparator greatequal     : 2
  11-bit comparator less           : 3
  10-bit comparator greatequal     : 2
  10-bit comparator less           : 3
  8-bit comparator equal           : 1
  3-bit comparator less            : 1
  4-bit comparator equal           : 1
  12-bit comparator less           : 4
  12-bit comparator equal          : 1
  12-bit comparator greater        : 2
  12-bit comparator greatequal     : 4

Design Statistics
# IOs                              : 97

Cell Usage :
# BELS                             : 2005
#      GND                         : 1
#      LUT1                        : 224
#      LUT2                        : 256
#      LUT3                        : 396
#      LUT4                        : 370
#      MUXCY                       : 369
#      MUXF5                       : 67
#      VCC                         : 1
#      XORCY                       : 321
# FlipFlops/Latches                : 467
#      FD                          : 65
#      FDC                         : 125
#      FDCE                        : 140
#      FDCP                        : 4
#      FDE                         : 65
#      FDP                         : 8
#      FDR                         : 1
#      FDRE                        : 21
#      LD                          : 18
#      LDC                         : 19
#      LDP                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 96
#      IBUF                        : 2
#      IOBUF                       : 32
#      OBUF                        : 51
#      OBUFT                       : 11
=========================================================================


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
inst_lzw_mux1_I__n0001:O           | NONE(*)(inst_lzw_mux1_o_1)| 16    |
halfclk:Q                          | NONE                   | 87    |
halfclk_3:Q                        | NONE                   | 86    |
I_memsel_1__n0002:O                | NONE(*)(memsel_0)      | 2     |
halfclk_1:Q                        | NONE                   | 87    |
halfclk_2:Q                        | NONE                   | 86    |
inst_prgramdacver2_gray_cnt_FFD2:Q | NONE                   | 43    |
inst_vgamem_hsyncb:Q               | NONE                   | 12    |
inst_vgamem_I_curraddr_19__n0004:O | NONE(*)(inst_vgamem_curraddr_13)| 40    |
clk                                | BUFGP                  | 32    |
-----------------------------------+------------------------+-------+
(*) These 3 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 28.929ns (Maximum Frequency: 34.567MHz)
   Minimum input arrival time before clock: 16.034ns
   Maximum output required time after clock: 31.454ns
   Maximum combinational path delay: 23.122ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'halfclk_2:Q'
Delay:               28.929ns (Levels of Logic = 40)
  Source:            inst_headers_reg_data_data_0
  Destination:       inst_headers_reg_inaddr_Data_19
  Source Clock:      halfclk_2:Q rising
  Destination Clock: halfclk_2:Q rising

  Data Path: inst_headers_reg_data_data_0 to inst_headers_reg_inaddr_Data_19
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FDCE:C->Q             19   1.065   2.790  inst_headers_reg_data_data_0 (inst_headers_reg_data_data_0)
    LUT3:I1->O             1   0.573   1.035  I_inst_prgramdacver2__n0042 (N822)
    LUT1:I0->O             2   0.573   0.000  inst_prgramdacver2_Msub_maxcolor10_inst_lut2_154 (inst_prgramdacver2_Msub_maxc
olor10_inst_lut2_154)
    MUXCY:S->O             1   0.653   0.000  inst_prgramdacver2_Msub_maxcolor10_inst_cy_164 (inst_prgramdacver2_Msub_maxcol
or10_inst_cy_164)
    MUXCY:CI->O            1   0.044   0.000  inst_prgramdacver2_Msub_maxcolor10_inst_cy_165 (inst_prgramdacver2_Msub_maxcol
or10_inst_cy_165)
    MUXCY:CI->O            1   0.044   0.000  inst_prgramdacver2_Msub_maxcolor10_inst_cy_166 (inst_prgramdacver2_Msub_maxcol
or10_inst_cy_166)
    MUXCY:CI->O            1   0.044   0.000  inst_prgramdacver2_Msub_maxcolor10_inst_cy_167 (inst_prgramdacver2_Msub_maxcol
or10_inst_cy_167)
    MUXCY:CI->O            1   0.044   0.000  inst_prgramdacver2_Msub_maxcolor10_inst_cy_168 (inst_prgramdacver2_Msub_maxcol
or10_inst_cy_168)
    MUXCY:CI->O            0   0.044   0.000  inst_prgramdacver2_Msub_maxcolor10_inst_cy_169 (inst_prgramdacver2_Msub_maxcol
or10_inst_cy_169)
    XORCY:CI->O            1   0.418   1.035  inst_prgramdacver2_Msub_maxcolor10_inst_sum_118 (N1339)
    LUT4:I3->O             1   0.573   0.000  inst_prgramdacver2_Mcompar__n0019_inst_lut4_3 (inst_prgramdacver2_Mcompar__n00
19_inst_lut4_3)
    MUXCY:S->O             5   0.653   1.566  inst_prgramdacver2_Mcompar__n0019_inst_cy_45 (N680)
    LUT3:I1->O             6   0.573   1.665  I_paldoneheaders (N688)
    LUT4:I1->O             1   0.573   1.035  inst_headers_I_8_LUT_53 (inst_headers_N549)
    LUT3:I0->O             1   0.573   1.035  inst_headers_I_7_LUT_11 (inst_headers_N553)
    LUT3:I1->O             6   0.573   1.665  inst_headers_I_sel_inaddr_addend_0 (inst_headers_N556)
    LUT3:I0->O             9   0.573   1.908  inst_headers_mux_addend_inaddr_I_XXL_150 (inst_headers_mux_addend_inaddr_N183)

    LUT4:I1->O             1   0.573   1.035  inst_headers_mux_addend_inaddr_I_2_LUT_30 (N29402)
    LUT4:I0->O             1   0.573   1.035  inst_headers_mux_addend_inaddr_I_o_0 (inst_headers_N735)
    LUT2:I1->O             2   0.573   0.000  inst_headers_adder_inaddr_Madd_s_inst_lut2_59 (inst_headers_adder_inaddr_Madd_
s_inst_lut2_59)
    MUXCY:S->O             1   0.653   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_69 (inst_headers_adder_inaddr_Madd_s_
inst_cy_69)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_70 (inst_headers_adder_inaddr_Madd_s_
inst_cy_70)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_71 (inst_headers_adder_inaddr_Madd_s_
inst_cy_71)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_72 (inst_headers_adder_inaddr_Madd_s_
inst_cy_72)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_73 (inst_headers_adder_inaddr_Madd_s_
inst_cy_73)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_74 (inst_headers_adder_inaddr_Madd_s_
inst_cy_74)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_75 (inst_headers_adder_inaddr_Madd_s_
inst_cy_75)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_76 (inst_headers_adder_inaddr_Madd_s_
inst_cy_76)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_77 (inst_headers_adder_inaddr_Madd_s_
inst_cy_77)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_78 (inst_headers_adder_inaddr_Madd_s_
inst_cy_78)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_79 (inst_headers_adder_inaddr_Madd_s_
inst_cy_79)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_80 (inst_headers_adder_inaddr_Madd_s_
inst_cy_80)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_81 (inst_headers_adder_inaddr_Madd_s_
inst_cy_81)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_82 (inst_headers_adder_inaddr_Madd_s_
inst_cy_82)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_83 (inst_headers_adder_inaddr_Madd_s_
inst_cy_83)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_84 (inst_headers_adder_inaddr_Madd_s_
inst_cy_84)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_85 (inst_headers_adder_inaddr_Madd_s_
inst_cy_85)
    MUXCY:CI->O            1   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_86 (inst_headers_adder_inaddr_Madd_s_
inst_cy_86)
    MUXCY:CI->O            0   0.044   0.000  inst_headers_adder_inaddr_Madd_s_inst_cy_87 (inst_headers_adder_inaddr_Madd_s_
inst_cy_87)
    XORCY:CI->O            1   0.418   1.035  inst_headers_adder_inaddr_Madd_s_inst_sum_36 (inst_headers_N744)
    LUT3:I0->O             1   0.573   0.000  inst_headers_mux_inaddr_I_o_19 (inst_headers_N764)
    FDCE:D                     0.342          inst_headers_reg_inaddr_Data_19
    ----------------------------------------
    Total                     28.929ns (12.090ns logic, 16.839ns route)
                                       (41.8% logic, 58.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'halfclk_2:Q'
Offset:              16.034ns (Levels of Logic = 7)
  Source:            resetl
  Destination:       inst_headers_reg_blksize_data_0
  Destination Clock: halfclk_2:Q rising

  Data Path: resetl to inst_headers_reg_blksize_data_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O             14   0.768   2.340  resetl_IBUF (resetl_IBUF)
    LUT2:I0->O             1   0.573   1.035  inst_vgamem_I_0_LUT_9 (inst_vgamem_N324)
    LUT4:I3->O            40   0.573   3.780  inst_vgamem_I_curraddr_19__n0004 (inst_vgamem_N326)
    LUT4:I3->O             1   0.573   0.000  inst_memreadmux_Mmux_memaddr_inst_lut3_151 (inst_memreadmux_Mmux_memaddr_xstma
cro_int_tempname218)
    MUXF5:I1->O           18   0.134   2.700  inst_memreadmux_Mmux_memaddr_inst_mux_f5_67 (N553)
    LUT4:I1->O            11   0.573   2.070  I_inst_memreadmux_Mmux_readdata_I15_Result (N763)
    LUT3:I2->O             1   0.573   0.000  inst_headers_mux_blksize_I_o_0 (inst_headers_N799)
    FDCE:D                     0.342          inst_headers_reg_blksize_data_0
    ----------------------------------------
    Total                     16.034ns (4.109ns logic, 11.925ns route)
                                       (25.6% logic, 74.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'halfclk_1:Q'
Offset:              31.454ns (Levels of Logic = 25)
  Source:            inst_headers_reg_width_low_data_1
  Destination:       ramdacdata_0
  Source Clock:      halfclk_1:Q rising

  Data Path: inst_headers_reg_width_low_data_1 to ramdacdata_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FDCE:C->Q              2   1.065   1.206  inst_headers_reg_width_low_data_1 (inst_headers_reg_width_low_data_1)
    LUT1:I0->O             1   0.573   0.000  inst_vgamem_I_INV_imwidth_1 (inst_vgamem_N302)
    MUXCY:S->O             1   0.653   0.000  inst_vgamem_Madd_blankwidth_inst_cy_154 (inst_vgamem_Madd_blankwidth_inst_cy_1
54)
    XORCY:CI->O            2   0.418   1.206  inst_vgamem_Madd_blankwidth_inst_sum_103 (inst_vgamem_N665)
    LUT2:I1->O             1   0.573   0.000  inst_vgamem_Madd__n0019_inst_lut2_194 (inst_vgamem_Madd__n0019_inst_lut2_194)
    MUXCY:S->O             1   0.653   0.000  inst_vgamem_Madd__n0019_inst_cy_204 (inst_vgamem_Madd__n0019_inst_cy_204)
    XORCY:CI->O            1   0.418   1.035  inst_vgamem_Madd__n0019_inst_sum_153 (inst_vgamem_N686)
    LUT1:I0->O             1   0.573   0.000  inst_vgamem_Msub_rightedge_inst_lut2_155 (inst_vgamem_Msub_rightedge_inst_lut2
_155)
    MUXCY:S->O             1   0.653   0.000  inst_vgamem_Msub_rightedge_inst_cy_165 (inst_vgamem_Msub_rightedge_inst_cy_165
)
    XORCY:CI->O            1   0.418   1.035  inst_vgamem_Msub_rightedge_inst_sum_114 (inst_vgamem_N654)
    LUT2:I1->O             1   0.573   0.000  inst_vgamem_Mcompar__n0030_inst_lut2_14 (inst_vgamem_Mcompar__n0030_inst_lut2_
14)
    MUXCY:S->O             1   0.653   0.000  inst_vgamem_Mcompar__n0030_inst_cy_14 (inst_vgamem_Mcompar__n0030_inst_cy_14)
    MUXCY:CI->O            1   0.044   0.000  inst_vgamem_Mcompar__n0030_inst_cy_15 (inst_vgamem_Mcompar__n0030_inst_cy_15)
    MUXCY:CI->O            1   0.044   0.000  inst_vgamem_Mcompar__n0030_inst_cy_16 (inst_vgamem_Mcompar__n0030_inst_cy_16)
    MUXCY:CI->O            1   0.044   0.000  inst_vgamem_Mcompar__n0030_inst_cy_17 (inst_vgamem_Mcompar__n0030_inst_cy_17)