__projnav.log

vhdl code for GIF Image Viewer

ISE Auto-Make Log File
-----------------------

Updating: Generate Programming File

Starting: 'exewrap @__gif_2prj_exewrap.rsp'


Creating TCL Process
Done: completed successfully.

Starting: 'exewrap -tapkeep -mode pipe -tcl -command C:/Xilinx/data/projnav/_filesAllClean.tcl _XSTClean.rsp 0'


Creating TCL Process
Cleaning Up Project
Finished cleaning up project
Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -command C:/Xilinx/bin/nt/xst.exe -ifn gif.xst -ofn gif.syr'


Starting: 'C:/Xilinx/bin/nt/xst.exe -ifn gif.xst -ofn gif.syr '


Release 4.1i - xst E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.03 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter overwrite set to YES
CPU : 0.00 / 0.03 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.03 s | Elapsed : 0.00 / 0.00 s
 
--> =========================================================================
---- Source Parameters
Input Format                       : VHDL
Input File Name                    : gif.prj

---- Target Parameters
Target Device                      : xcv50-pq240-6
Output File Name                   : gif
Output Format                      : NGC
Target Technology                  : virtex

---- Source Options
Entity Name                        : gif
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
ROM Extraction                     : Yes
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Add Generic Clock Buffer(BUFG)     : 4
Global Maximum Fanout              : 100
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Speed Grade                        : 6

---- General Options
Optimization Criterion             : Area
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : No
Global Optimization                : AllClockNets
Write Timing Constraints           : No
Incremental Synthesis              : NO

=========================================================================

Compiling vhdl file E:/GIF.3.21m/reg.vhd in Library work.
Architecture Behavioral of Entity Reg is up to date.
Compiling vhdl file E:/GIF.3.21m/mux2.vhd in Library work.
Architecture Behavioral of Entity Mux2 is up to date.
Compiling vhdl file E:/GIF.3.21m/adder.vhd in Library work.
Architecture Behavioral of Entity Adder is up to date.
Compiling vhdl file E:/GIF.3.21m/mux6.vhd in Library work.
Architecture Behavioral of Entity Mux6 is up to date.
Compiling vhdl file E:/GIF.3.21m/decoder3.vhd in Library work.
Architecture Behavioral of Entity Decoder3 is up to date.
Compiling vhdl file E:/GIF.3.21m/counter2.vhd in Library work.
Architecture Behavioral of Entity Counter2 is up to date.
Compiling vhdl file E:/GIF.3.21m/counter3.vhd in Library work.
Architecture Behavioral of Entity Counter3 is up to date.
Compiling vhdl file E:/GIF.3.21m/counter.vhd in Library work.
Architecture Behavioral of Entity Counter is up to date.
Compiling vhdl file E:/GIF.3.21m/register1.vhd in Library work.
Architecture Behavioral of Entity Register1 is up to date.
Compiling vhdl file E:/GIF.3.21m/register2.vhd in Library work.
Architecture Behavioral of Entity Register2 is up to date.
Compiling vhdl file E:/GIF.3.21m/mux5.vhd in Library work.
Architecture Behavioral of Entity Mux5 is up to date.
Compiling vhdl file E:/GIF.3.21m/lzw.vhd in Library work.
Architecture Structural of Entity Lzw is up to date.
Compiling vhdl file E:/GIF.3.21m/headers.vhd in Library work.
Architecture Behavioral of Entity Headers is up to date.
Compiling vhdl file E:/GIF.3.21m/prgramdac.vhd in Library work.
Architecture Prgramdacver2_arch of Entity Prgramdacver2 is up to date.
Compiling vhdl file E:/GIF.3.21m/vgacore.vhd in Library work.
Architecture Vgacore_arch of Entity Vgacore is up to date.
Compiling vhdl file E:/GIF.3.21m/memreadmux.vhd in Library work.
Architecture Behavioral of Entity Memreadmux is up to date.
Compiling vhdl file E:/GIF.3.21m/gif.vhd in Library work.
Entity <Gif> (Architecture <Behavioral>) compiled.

Analyzing Entity <gif> (Architecture <Behavioral>).
Entity <gif> analyzed. Unit <gif> generated.

Analyzing Entity <lzw> (Architecture <structural>).
Entity <lzw> analyzed. Unit <lzw> generated.

Analyzing Entity <headers> (Architecture <behavioral>).
Entity <headers> analyzed. Unit <headers> generated.

Analyzing Entity <prgramdacver2> (Architecture <prgramdacver2_arch>).
WARNING:Xst:819 - E:/GIF.3.21m/prgramdac.vhd (Line 188). The following signals are missing in the process sensitivity list:
   prgrgb, maxcolor, colourcnt.
Entity <prgramdacver2> analyzed. Unit <prgramdacver2> generated.

Analyzing Entity <vgacore> (Architecture <vgacore_arch>).
WARNING:Xst:819 - E:/GIF.3.21m/vgacore.vhd (Line 185). The following signals are missing in the process sensitivity list:
   leftedge, rightedge, topedge, bottomedge.
WARNING:Xst:819 - E:/GIF.3.21m/vgacore.vhd (Line 201). The following signals are missing in the process sensitivity list:
   vsyncb, outofbound, curraddr.
Entity <vgacore> analyzed. Unit <vgacore> generated.

Analyzing Entity <memreadmux> (Architecture <behavioral>).
Entity <memreadmux> analyzed. Unit <memreadmux> generated.

Analyzing generic Entity <counter2> (Architecture <behavioral>).
	size = 20
WARNING:Xst:819 - E:/GIF.3.21m/counter2.vhd (Line 20). The following signals are missing in the process sensitivity list:
   indata.
Entity <counter2> analyzed. Unit <counter2> generated.

Analyzing generic Entity <counter2> (Architecture <behavioral>).
	size = 12
WARNING:Xst:819 - E:/GIF.3.21m/counter2.vhd (Line 20). The following signals are missing in the process sensitivity list:
   indata.
Entity <counter2> analyzed. Unit <counter20> generated.

Analyzing generic Entity <counter3> (Architecture <behavioral>).
	size = 12
Entity <counter3> analyzed. Unit <counter3> generated.

Analyzing generic Entity <counter> (Architecture <behavioral>).
	size = 4
Entity <counter> analyzed. Unit <counter> generated.

Analyzing Entity <register1> (Architecture <behavioral>).
Entity <register1> analyzed. Unit <register1> generated.

Analyzing Entity <register2> (Architecture <behavioral>).
WARNING:Xst:819 - E:/GIF.3.21m/register2.vhd (Line 22). The following signals are missing in the process sensitivity list:
   indata.
Entity <register2> analyzed. Unit <register2> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 16
Entity <reg> analyzed. Unit <reg> generated.

Analyzing generic Entity <mux5> (Architecture <behavioral>).
	size = 16
Entity <mux5> analyzed. Unit <mux5> generated.

Analyzing generic Entity <mux6> (Architecture <behavioral>).
	size = 20
Entity <mux6> analyzed. Unit <mux6> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 20
Entity <reg> analyzed. Unit <reg1> generated.

Analyzing generic Entity <mux2> (Architecture <behavioral>).
	size = 20
Entity <mux2> analyzed. Unit <mux2> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 8
Entity <reg> analyzed. Unit <reg2> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 4
Entity <reg> analyzed. Unit <reg3> generated.

Analyzing generic Entity <reg> (Architecture <behavioral>).
	size = 2
Entity <reg> analyzed. Unit <reg4> generated.

Analyzing generic Entity <adder> (Architecture <behavioral>).
	size = 20
Entity <adder> analyzed. Unit <adder> generated.

Analyzing generic Entity <adder> (Architecture <behavioral>).
	size = 8
Entity <adder> analyzed. Unit <adder5> generated.

Analyzing generic Entity <mux2> (Architecture <behavioral>).
	size = 8
Entity <mux2> analyzed. Unit <mux26> generated.

Analyzing generic Entity <adder> (Architecture <behavioral>).
	size = 9
Entity <adder> analyzed. Unit <adder7> generated.

Analyzing Entity <decoder3> (Architecture <behavioral>).
Entity <decoder3> analyzed. Unit <decoder3> generated.


Synthesizing Unit <decoder3>.
    Related source file is E:/GIF.3.21m/decoder3.vhd.
    Found 1-of-8 decoder for signal <o>.
    Summary:
	inferred   1 Decoder(s).
Unit <decoder3> synthesized.


Synthesizing Unit <adder7>.
    Related source file is E:/GIF.3.21m/adder.vhd.
    Found 9-bit adder for signal <s>.
WARNING:Xst:647 - Input <b<8>> is never used.
WARNING:Xst:647 - Input <b<7>> is never used.
WARNING:Xst:647 - Input <b<6>> is never used.
WARNING:Xst:647 - Input <b<5>> is never used.
WARNING:Xst:647 - Input <b<4>> is never used.
WARNING:Xst:647 - Input <b<3>> is never used.
WARNING:Xst:647 - Input <b<2>> is never used.
WARNING:Xst:647 - Input <b<1>> is never used.
WARNING:Xst:647 - Input <b<0>> is never used.
    Summary:
	inferred   1 Adder/Subtracter(s).
Unit <adder7> synthesized.


Synthesizing Unit <mux26>.
    Related source file is E:/GIF.3.21m/mux2.vhd.
Unit <mux26> synthesized.


Synthesizing Unit <adder5>.
    Related source file is E:/GIF.3.21m/adder.vhd.
    Found 8-bit adder for signal <s>.
WARNING:Xst:647 - Input <a<7>> is never used.
WARNING:Xst:647 - Input <a<6>> is never used.
WARNING:Xst:647 - Input <a<5>> is never used.
WARNING:Xst:647 - Input <a<4>> is never used.
WARNING:Xst:647 - Input <a<3>> is never used.
WARNING:Xst:647 - Input <a<2>> is never used.
WARNING:Xst:647 - Input <a<1>> is never used.
WARNING:Xst:647 - Input <a<0>> is never used.
    Summary:
	inferred   1 Adder/Subtracter(s).
Unit <adder5> synthesized.


Synthesizing Unit <adder>.
    Related source file is E:/GIF.3.21m/adder.vhd.
    Found 20-bit adder for signal <s>.
    Summary:
	inferred   1 Adder/Subtracter(s).
Unit <adder> synthesized.