counter2.vhd

vhdl code for GIF Image Viewer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter2 is
    generic ( size : integer := 16);
    Port (cop: IN std_logic_vector(1 downto 0);
	 			reset: IN std_logic;
				clk: IN std_logic;
				indata: IN std_logic_vector(size-1 downto 0);
				outdata: OUT std_logic_vector(size-1 downto 0)
	 );
end counter2;

architecture Behavioral of counter2 is

begin

PROCESS (clk)
variable output, input: integer;
begin
input := conv_integer(indata);

if (clk'EVENT and clk='1') THEN
	if (reset = '1') THEN output := input; END IF;
    if (cop = "00") THEN output := output; END IF;
	if (cop = "01") THEN output := output + 1; END IF;
	if (cop = "10") THEN output := output - 1; END IF;
	if (cop = "11") THEN output := input; END IF;

end if;

outdata <= conv_std_logic_vector(output, size);

end process;

end Behavioral;