📄 prgramdacver2.vhi
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-- VHDL Instantiation Created from source file prgramdacver2.vhd -- 18:34:21 03/15/2004
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
COMPONENT prgramdacver2
PORT(
clk : IN std_logic;
rstn : IN std_logic;
start : IN std_logic;
readData : IN std_logic_vector(7 downto 0);
startAddr : IN std_logic_vector(19 downto 0);
tableSize : IN std_logic_vector(2 downto 0);
RS : INOUT std_logic_vector(2 downto 0);
data : INOUT std_logic_vector(7 downto 0);
done : OUT std_logic;
WRn : OUT std_logic;
RDn : OUT std_logic;
oen : OUT std_logic;
wen : OUT std_logic;
readAddr : OUT std_logic_vector(19 downto 0)
);
END COMPONENT;
Inst_prgramdacver2: prgramdacver2 PORT MAP(
clk => ,
rstn => ,
start => ,
done => ,
WRn => ,
RDn => ,
RS => ,
data => ,
oen => ,
wen => ,
readAddr => ,
readData => ,
startAddr => ,
tableSize =>
);
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