📄 lzw_beh.vhi
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-- VHDL Instantiation Created from source file lzw_beh.vhd -- 17:28:12 03/21/2004
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
COMPONENT lzw_beh
PORT(
clk : IN std_logic;
start : IN std_logic;
readData : IN std_logic_vector(15 downto 0);
codesize : IN std_logic_vector(7 downto 0);
addr : OUT std_logic_vector(19 downto 0);
writeData : OUT std_logic_vector(15 downto 0);
oen : OUT std_logic;
wen : OUT std_logic;
done : OUT std_logic
);
END COMPONENT;
Inst_lzw_beh: lzw_beh PORT MAP(
clk => ,
start => ,
readData => ,
codesize => ,
addr => ,
writeData => ,
oen => ,
wen => ,
done =>
);
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