gif.vhd

vhdl code for GIF Image Viewer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gif is
    Port (
	 	clk : in std_logic;
		resetL : in std_logic;
        start : in std_logic;

		ldata, rdata : inout std_logic_vector(15 downto 0);
		lcen, rcen : out std_logic;
		loen, roen : out std_logic;
		lwen, rwen : out std_logic;
		laddr, raddr : out std_logic_vector(18 downto 0);

		ramdacdata : inout std_logic_vector(7 downto 0);
		rdN, wrN : out std_logic;
		rs : inout std_logic_vector(2 downto 0);
		pixelclk : out std_logic;
		hsyncb, vsyncb : out std_logic;
		pblank : out std_logic;

		triste : out std_logic
	 );
end gif;

architecture Behavioral of gif is
	COMPONENT headers
	PORT(
		clk : IN std_logic;
		rstL : IN std_logic;
		start : IN std_logic;
		paletteProgDone : IN std_logic;
		readData : IN std_logic_vector(15 downto 0);          
		addr : OUT std_logic_vector(19 downto 0);
		writeData : OUT std_logic_vector(15 downto 0);
		oen : OUT std_logic;
		wen : OUT std_logic;
		height : OUT std_logic_vector(9 downto 0);
		width : OUT std_logic_vector(9 downto 0);
		codesize : OUT std_logic_vector(3 downto 0);
		coltablecode : OUT std_logic_vector(2 downto 0);
		startPaletteProg : OUT std_logic;
		done : OUT std_logic
		);
	END COMPONENT;
	component lzw is
    Port ( start,resetin, clk : in std_logic;
           addr : out std_logic_vector(19 downto 0);
           rddata : in std_logic_vector(15 downto 0);
           wrdata : out std_logic_vector(15 downto 0);
           wen : out std_logic;
           oen, done1: out std_logic);
	end component;
	COMPONENT prgramdacver2
	PORT(
        clk: in STD_LOGIC;									-- Clock
        rstn: in STD_LOGIC;									-- Asynchronous active low reset
        start: in STD_LOGIC;								-- Start signal
        done: out STD_LOGIC;								-- Asserted when programming is finished
        WRn: out STD_LOGIC;									-- Write line to RAMDAC (active low)
        RDn: out STD_LOGIC;									-- Read line to RAMDAC (active low)
        RS: inout STD_LOGIC_VECTOR (2 downto 0);			-- Register select lines to the RAMDAC
        data: inout STD_LOGIC_VECTOR (7 downto 0);			-- Bidirectional data line to RAMDAC
		  oen: out STD_LOGIC;
		  wen: out STD_LOGIC;
		  readAddr: out STD_LOGIC_VECTOR(19 downto 0);
		  readData: in STD_LOGIC_VECTOR(15 downto 0);
		  startAddr : in STD_LOGIC_VECTOR(19 downto 0);
          tableSize : in STD_LOGIC_VECTOR(2 downto 0)
		);
	END COMPONENT;
	COMPONENT vgacore
	PORT(
		reset: in std_logic;						-- asynchronous active low reset
		clock: in std_logic;						-- clock
		imwidth, imheight : in std_logic_vector(9 downto 0);

		pixelclk : out std_logic;
		pblank : out std_logic;
		hsync: out std_logic;					-- horizontal (line) sync
		vsync: out std_logic;						-- vertical (frame) sync

		readAddr : out std_logic_vector(19 downto 0);
		oeb, web : out std_logic
		);
	END COMPONENT;
	COMPONENT memreadmux
	PORT(
		paletteAddr : IN std_logic_vector(19 downto 0);
		paletteWriteData : IN std_logic_vector(15 downto 0);
		paletteOEN : IN std_logic;
		paletteWEN : IN std_logic;
		lzwAddr : IN std_logic_vector(19 downto 0);
		lzwWriteData : IN std_logic_vector(15 downto 0);
		lzwOEN : IN std_logic;
		lzwWEN : IN std_logic;
		headersAddr : IN std_logic_vector(19 downto 0);
		headersWriteData : IN std_logic_vector(15 downto 0);
		headersOEN : IN std_logic;
		headersWEN : IN std_logic;
		vgaAddr : IN std_logic_vector(19 downto 0);
		vgaWriteData : IN std_logic_vector(15 downto 0);
		vgaOEN : IN std_logic;
		vgaWEN : IN std_logic;
		sel : IN std_logic_vector(1 downto 0);    
		lData : INOUT std_logic_vector(15 downto 0);
		rData : INOUT std_logic_vector(15 downto 0);      
		lAddr : OUT std_logic_vector(18 downto 0);
		lOEN : OUT std_logic;
		lWEN : OUT std_logic;
		lCEN : OUT std_logic;
		rAddr : OUT std_logic_vector(18 downto 0);
		rOEN : OUT std_logic;
		rWEN : OUT std_logic;
		rCEN : OUT std_logic;
		paletteReadData : OUT std_logic_vector(15 downto 0);
		lzwReadData : OUT std_logic_vector(15 downto 0);
		headersReadData : OUT std_logic_vector(15 downto 0);
		vgaReadData : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

	constant CONST_CONNECT_PALETTE : STD_LOGIC_VECTOR(1 downto 0) := "00";
	constant CONST_CONNECT_LZW : STD_LOGIC_VECTOR(1 downto 0) := "01";
	constant CONST_CONNECT_HEADERS : STD_LOGIC_VECTOR(1 downto 0) := "10";
	constant CONST_CONNECT_VGA : STD_LOGIC_VECTOR(1 downto 0) := "11";

	signal reset, startLzw, startHeaders, startPalette, lzwDone, headersDone,
			 paletteDone, paldoneHeaders, palstartHeaders : std_logic;
	signal lzwOen, lzwWen, headersOen, headersWen, vgaOen, vgaWen, paletteOen, paletteWen : std_logic;
	signal lzwAddr, headersAddr, vgaAddr, paletteAddr : std_logic_vector(19 downto 0);
	signal lzwReadData, lzwWriteData, headersReadData, headersWriteData,
			 vgaReadData, vgaWriteData, paletteReadData, paletteWriteData
			 	: std_logic_vector(15 downto 0);
	signal coltablecode : std_logic_vector(2 downto 0);
	signal memsel : std_logic_vector(1 downto 0);
    signal imheight, imwidth : std_logic_vector(9 downto 0);
    signal codesize : std_logic_vector(3 downto 0);

	type stateT is (
		stIdle, stWaitHeaders, stWaitPalette, stWaitLzw, stStartPalette1, stStartPalette2, 
        stStartPalette3, stStartLzw, stStartHeaders, stDone
	);
	signal presState, nextState : stateT;

    signal halfclk : std_logic;
begin

    triste <= '1';

    process (clk, reset)
    begin
        if (reset = '1') then
            halfclk <= clk;
        elsif (clk'event and clk = '1') then
            halfclk <= not halfclk;
        end if;
    end process;

	process (clk, resetL)
	begin
		if (resetL = '0') then
			presState <= stIdle;
		elsif (clk'event and clk = '1') then
			presState <= nextState;
		end if;
	end process;

	process (presState, start, paletteDone, headersDone, lzwDone, palstartHeaders)
	begin
		startHeaders <= '0';
		startLzw <= '0';
		startPalette <= '0';
		paldoneHeaders <= '0';

		case presState is
			when stIdle =>
				memsel <= CONST_CONNECT_VGA;
				if start = '0' then
					startHeaders <= '1';
					nextState <= stStartHeaders;
				else
					nextState <= stIdle;
				end if;
            when stStartHeaders =>
                startHeaders <= '1';
                nextState <= stWaitHeaders;
    		when stWaitHeaders =>
				memsel <= CONST_CONNECT_HEADERS;
				if headersDone = '1' then
					startLzw <= '1';
					nextState <= stStartLzw;
				elsif palstartHeaders = '1' then
					startPalette <= '1';
					nextState <= stStartPalette1;
				else
					nextState <= stWaitHeaders;
				end if;
            when stStartPalette1 =>
                startPalette <= '1';
                nextState <= stStartPalette2;
            when stStartPalette2 =>
                startPalette <= '1';
                nextState <= stStartPalette3;
            when stStartPalette3 =>
                startPalette <= '1';
                nextState <= stWaitPalette;
			when stWaitPalette =>
				memsel <= CONST_CONNECT_PALETTE;
				if paletteDone = '1' then
					paldoneHeaders <= '1';
					nextState <= stWaitHeaders;
				else
					nextState <= stWaitPalette;
				end if;
            when stStartLzw =>
                startLzw <= '1';
                nextState <= stWaitLzw;
			when stWaitLzw =>
				memsel <= CONST_CONNECT_LZW;
				if lzwDone = '1' then
					nextState <= stDone;
				else
					nextState <= stWaitLzw;
				end if;
            when stDone =>
                nextState <= stDone;

		end case;
	end process;

	reset <= not resetL;

	Inst_lzw : lzw PORT MAP(
		start => startLzw,
		resetin => reset,
		clk => halfclk,
		addr => lzwAddr,
		rddata => lzwReadData,
		wrdata => lzwWriteData,
		wen => lzwWen,
		oen => lzwOen,
        done1 => lzwDone
	);

	Inst_headers: headers PORT MAP(
		clk => halfclk,
		rstL => resetL,
		start => startHeaders,
		paletteProgDone => paldoneHeaders,
		readData => headersReadData,
		addr => headersAddr,
		writeData => headersWriteData,
		oen => headersOen,
		wen => headersWen,
		height => imHeight,
		width => imWidth,
		codesize => codesize,
		coltablecode => coltablecode,
		startPaletteProg => palstartHeaders,
		done => headersDone
	);

	Inst_prgramdacver2: prgramdacver2 PORT MAP(
		clk => clk,
		rstn => resetL,
		start => startPalette,
		done => paletteDone,
		WRn => WRn,
		RDn => RDn,
		RS => RS,
		data => ramdacdata,
		oen => paletteOen,
		wen => paletteWen,
		readAddr => paletteAddr,
		readData => paletteReadData,
		startAddr => headersAddr,
		tableSize => coltablecode
	);

	Inst_vgamem: vgacore PORT MAP(
		reset => resetL,
		clock => clk,
		hsync => hsyncb,
		vsync => vsyncb,
		readAddr => vgaAddr,
		oeb => vgaOen,
		web => vgaWen,
		pixelclk => pixelclk,
		pblank => pblank,
		imwidth => imWidth,
		imheight => imHeight
	);

	Inst_memreadmux: memreadmux PORT MAP(
		lAddr => laddr,
		lData => ldata,
		lOEN => loen,
		lWEN => lwen,
		lCEN => lcen,
		rAddr => raddr,
		rData => rdata,
		rOEN => roen,
		rWEN => rwen,
		rCEN => rcen,
		paletteAddr => paletteAddr,
		paletteReadData => paletteReadData,
		paletteWriteData => x"0000",
		paletteOEN => paletteOen,
		paletteWEN => paletteWen,
		lzwAddr => lzwAddr,
		lzwReadData => lzwReadData,
		lzwWriteData => lzwWriteData,
		lzwOEN => lzwOen,
		lzwWEN => lzwWen,
		headersAddr => headersAddr,
		headersReadData => headersReadData,
		headersWriteData => headersWriteData,
		headersOEN => headersOen,
		headersWEN => headersWen,
		vgaAddr => vgaAddr,
		vgaReadData => vgaReadData,
		vgaWriteData => x"0000",
		vgaOEN => vgaOen,
		vgaWEN => vgaWen,
		sel => memsel
	);

end Behavioral;