📄 counter2.vhi
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-- VHDL Instantiation Created from source file counter2.vhd -- 14:27:50 03/14/2004
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
COMPONENT counter2
PORT(
cop : IN std_logic_vector(1 downto 0);
reset : IN std_logic;
clk : IN std_logic;
indata : IN std_logic_vector(11 downto 0);
outdata : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
Inst_counter2: counter2 PORT MAP(
cop => ,
reset => ,
clk => ,
indata => ,
outdata =>
);
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