📄 mux3.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux3 is
Generic ( size : integer := 8 );
Port ( d0 : in std_logic_vector(size-1 downto 0);
d1 : in std_logic_vector(size-1 downto 0);
d2 : in std_logic_vector(size-1 downto 0);
s : in std_logic_vector(1 downto 0);
o : out std_logic_vector(size-1 downto 0));
end mux3;
architecture Behavioral of mux3 is
begin
PROCESS (s, d0, d1, d2)
begin
IF (s = "00") THEN o <= d0;
ELSIF (s = "01") THEN o <= d1;
ELSE (s = "10") o <= d2;
END IF;
END PROCESS;
end Behavioral;
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