reg.vhi

vhdl code for GIF Image Viewer

-- VHDL Instantiation Created from source file reg.vhd -- 15:34:27 03/07/2004
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT reg
	PORT(
		d : IN std_logic_vector(7 downto 0);
		rstL : IN std_logic;
		clk : IN std_logic;
		ce : IN std_logic;          
		q : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	Inst_reg: reg PORT MAP(
		d => ,
		q => ,
		rstL => ,
		clk => ,
		ce => 
	);