register1.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity register1 is
    Port (clk, reset: in std_logic;
	 			cop: in std_logic_vector (1 downto 0);
				indata: in std_logic_vector (7 downto 0);
				outdata: out std_logic;
                temp: out std_logic_vector (7 downto 0)
			 );
end register1;

architecture Behavioral of register1 is

begin
process (clk)
variable data: std_logic_vector (7 downto 0);

begin

if (clk'EVENT and clk='1') THEN
    if (reset = '1') THEN data := "00000000"; end if;
	if (cop = "10") THEN 
		data(6 downto 0) := data(7 downto 1);
		data(7) := '0';
		end if;
	if (cop = "01") THEN data := indata; 
    elsif (cop = "00") then data := data; end if;
end if;
outdata <= data(0);
temp <= data;

end process;


end Behavioral;