hdrs_test.vhd

vhdl code for GIF Image Viewer

-- VHDL Test Bench Created from source file headers.vhd -- 19:29:50 03/19/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT headers_beh
	PORT(
		clk : IN std_logic;
		rstL : IN std_logic;
		start : IN std_logic;
		paletteProgDone : IN std_logic;
		readData : IN std_logic_vector(15 downto 0);          
		addr : OUT std_logic_vector(19 downto 0);
		writeData : OUT std_logic_vector(15 downto 0);
		oen : OUT std_logic;
		wen : OUT std_logic;
		height : OUT std_logic_vector(9 downto 0);
		width : OUT std_logic_vector(9 downto 0);
		codesize : OUT std_logic_vector(3 downto 0);
		coltablecode : OUT std_logic_vector(2 downto 0);
		startPaletteProg : OUT std_logic;
		done : OUT std_logic
		);
	END COMPONENT;
	COMPONENT memreadmux
	PORT(
		paletteAddr : IN std_logic_vector(19 downto 0);
		paletteWriteData : IN std_logic_vector(15 downto 0);
		paletteOEN : IN std_logic;
		paletteWEN : IN std_logic;
		lzwAddr : IN std_logic_vector(19 downto 0);
		lzwWriteData : IN std_logic_vector(15 downto 0);
		lzwOEN : IN std_logic;
		lzwWEN : IN std_logic;
		headersAddr : IN std_logic_vector(19 downto 0);
		headersWriteData : IN std_logic_vector(15 downto 0);
		headersOEN : IN std_logic;
		headersWEN : IN std_logic;
		vgaAddr : IN std_logic_vector(19 downto 0);
		vgaWriteData : IN std_logic_vector(15 downto 0);
		vgaOEN : IN std_logic;
		vgaWEN : IN std_logic;
		sel : IN std_logic_vector(1 downto 0);    
		lData : INOUT std_logic_vector(15 downto 0);
		rData : INOUT std_logic_vector(15 downto 0);      
		lAddr : OUT std_logic_vector(18 downto 0);
		lOEN : OUT std_logic;
		lWEN : OUT std_logic;
		lCEN : OUT std_logic;
		rAddr : OUT std_logic_vector(18 downto 0);
		rOEN : OUT std_logic;
		rWEN : OUT std_logic;
		rCEN : OUT std_logic;
		paletteReadData : OUT std_logic_vector(15 downto 0);
		lzwReadData : OUT std_logic_vector(15 downto 0);
		headersReadData : OUT std_logic_vector(15 downto 0);
		vgaReadData : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;
	component sram is
	    Generic (
		 		mem_words : integer := 524287;
				word_size : integer := 16;
	
				tAA : time := 15 ns;
				tACE : time := 15 ns;
				tOE : time := 7 ns;
				tOH : time := 3 ns;
				tCLZ : time := 1 ns;
				tCHZ : time := 7 ns;
				tOLZ : time := 1 ns;
				tOHZ : time := 7 ns;
	
				tCW : time := 10 ns;
				tAW : time := 10 ns;
				tAS : time := 0 ns;
				tWP1 : time := 10 ns;
				tWP2 : time := 15 ns;
				tAH : time := 0 ns;		-- unimplemented
				tWR : time := 0 ns;		-- unimplemented
				tDW : time := 7 ns;
				tDH : time := 0 ns;		-- unimplemented
				tWZ : time := 7 ns;
				tOW : time := 3 ns
		 );
	    Port ( addr : in std_logic_vector(18 downto 0);
	           ceN : in std_logic;
	           oeN : in std_logic;
	           weN : in std_logic;
				  load : in std_logic;
				  filename : in string(1 to 12);
				  load_addr : in natural;
	           data : inout std_logic_vector(15 downto 0);
				  violation : out std_logic
				  );
	end component;
	SIGNAL clk :  std_logic;
	SIGNAL rstL :  std_logic;
	SIGNAL start :  std_logic;
	SIGNAL paletteProgDone :  std_logic;
	SIGNAL readData :  std_logic_vector(15 downto 0);
	SIGNAL addr :  std_logic_vector(19 downto 0);
	signal laddr, raddr : std_logic_vector(18 downto 0);
	SIGNAL writeData, ldata, rdata :  std_logic_vector(15 downto 0);
	SIGNAL oen, loen, roen :  std_logic;
	SIGNAL wen, lwen, rwen, lcen, rcen, loadleft, loadright,
			 violationleft, violationright :  std_logic;
	SIGNAL height :  std_logic_vector(9 downto 0);
	SIGNAL width :  std_logic_vector(9 downto 0);
	SIGNAL codesize :  std_logic_vector(3 downto 0);
	SIGNAL coltablecode :  std_logic_vector(2 downto 0);
	SIGNAL startPaletteProg :  std_logic;
	SIGNAL done :  std_logic;
	signal filenameleft, filenameright : string(1 to 12);
	signal loadleftaddr, loadrightaddr : natural;
BEGIN

	uut: headers_beh PORT MAP(
		clk => clk,
		rstL => rstL,
		start => start,
		paletteProgDone => paletteProgDone,
		readData => readData,
		addr => addr,
		writeData => writeData,
		oen => oen,
		wen => wen,
		height => height,
		width => width,
		codesize => codesize,
		coltablecode => coltablecode,
		startPaletteProg => startPaletteProg,
		done => done
	);
	Inst_memreadmux: memreadmux PORT MAP(
		lAddr => laddr,
		lData => ldata,
		lOEN => loen,
		lWEN => lwen,
		lCEN => lcen,
		rAddr => raddr,
		rData => rdata,
		rOEN => roen,
		rWEN => rwen,
		rCEN => rcen,
		paletteAddr => x"00000",
		paletteReadData => open,
		paletteWriteData => x"0000",
		paletteOEN => '1',
		paletteWEN => '1',
		lzwAddr => x"00000",
		lzwReadData => open,
		lzwWriteData => x"0000",
		lzwOEN => '1',
		lzwWEN => '1',
		headersAddr => addr,
		headersReadData => readdata,
		headersWriteData => writedata,
		headersOEN => oen,
		headersWEN => wen,
		vgaAddr => x"00000",
		vgaReadData => open,
		vgaWriteData => x"0000",
		vgaOEN => '1',
		vgaWEN => '1',
		sel => "10"
	);

	lram : sram
	port map (
		addr => laddr,
		oen => loen,
		wen => lwen,
		cen => lcen,
		data => ldata,
		load => loadleft,
		load_addr => loadleftaddr,
		filename => filenameleft,
		violation => violationleft);

	rram : sram
	port map (
		addr => raddr,
		oen => roen,
		wen => rwen,
		cen => rcen,
		data => rdata,
		load => loadright,
		load_addr => loadrightaddr,
		filename => filenameright,
		violation => violationright);


-- *** Test Bench - User Defined Section ***
	process
		begin
			paletteprogdone <= '0';
			wait for 400 ns;
			paletteprogdone <= '1';
			wait for 20 ns;
			paletteprogdone <= '0';
			wait;
	end process;

   tb : PROCESS
   BEGIN
		loadleft <= '0';
		loadright <= '0';
		loadleftaddr <= 0;
		loadrightaddr <= 0;
		filenameleft <= "            ";
		filenameright <= "gifdata1.hex";
		start <= '0';
		rstL <= '0';

		loadright <= '1';
		wait for 10 ns;
		loadright <= '0';

		wait for 100 ns;
		rstL <= '1';
		wait for 100 ns;
		start <= '1';
		wait for 20 ns;
		start <= '0';
      wait; -- will wait forever
   END PROCESS;

	process
	begin
		clk <= '1';
		loop
			wait for 10 ns;
			clk <= not clk;
		end loop;
	end process;
-- *** End Test Bench - User Defined Section ***

END;