hssdrc_decoder_state.v

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv

//
// Project      : High-Speed SDRAM Controller with adaptive bank management and command pipeline
// 
// Project Nick : HSSDRC
// 
// Version      : 1.0-beta 
//  
// Revision     : $Revision: 1.1 $ 
// 
// Date         : $Date: 2008-03-06 13:52:43 $ 
// 
// Workfile     : hssdrc_decoder_state.v
// 
// Description  : sdram command sequence decoder
// 
// HSSDRC is licensed under MIT License
// 
// Copyright (c) 2007-2008, Denis V.Shekhalev ([e-mail]) 
// 
// Permission  is hereby granted, free of charge, to any person obtaining a copy of
// this  software  and  associated documentation files (the "Software"), to deal in
// the  Software  without  restriction,  including without limitation the rights to
// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
// the  Software, and to permit persons to whom the Software is furnished to do so,
// subject to the following conditions:
// 
// The  above  copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
// 
// THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
// FOR  A  PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
// COPYRIGHT  HOLDERS  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
// IN  AN  ACTION  OF  CONTRACT,  TORT  OR  OTHERWISE,  ARISING  FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//


`include "hssdrc_timescale.vh"

`include "hssdrc_timing.vh"
`include "hssdrc_define.vh"


module hssdrc_decoder_state (
  clk               ,
  reset             ,
  sclr              ,
  //
  ba_map_update     ,
  ba_map_clear      ,
  ba_map_pre_act_rw ,
  ba_map_act_rw     ,
  ba_map_rw         ,
  ba_map_all_close  ,
  //
  arb_write         ,
  arb_read          ,
  arb_refr          ,
  arb_rowa          ,
  arb_cola          ,
  arb_ba            ,
  arb_burst         ,
  arb_chid          ,
  arb_ready         ,
  //
  dec_pre_all       ,
  dec_refr          ,
  dec_pre           ,
  dec_act           ,
  dec_read          ,
  dec_write         ,  
  //
  dec_pre_all_enable,
  dec_refr_enable   ,
  dec_pre_enable    ,
  dec_act_enable    ,
  dec_read_enable   ,
  dec_write_enable  ,
  //
  dec_locked        ,
  dec_last          ,
  //
  dec_rowa          ,
  dec_cola          ,
  dec_ba            ,
  dec_chid          ,
  //
  dec_burst
  );

  input   wire  clk  ;
  input   wire  reset;
  input   wire  sclr ;

  //-------------------------------------------------------------------------------------------------- 
  // bank map interface 
  //-------------------------------------------------------------------------------------------------- 

  output  logic ba_map_update     ;
  output  logic ba_map_clear      ;
  input   wire  ba_map_pre_act_rw ;
  input   wire  ba_map_act_rw     ;
  input   wire  ba_map_rw         ;
  input   wire  ba_map_all_close  ;

  //-------------------------------------------------------------------------------------------------- 
  // interface from input arbiter 
  //-------------------------------------------------------------------------------------------------- 

  input   wire    arb_write ;
  input   wire    arb_read  ;
  input   wire    arb_refr  ;
  input   rowa_t  arb_rowa  ;
  input   cola_t  arb_cola  ;
  input   ba_t    arb_ba    ;  
  input   burst_t arb_burst ;
  input   chid_t  arb_chid  ;
  output  logic   arb_ready ;

  //-------------------------------------------------------------------------------------------------- 
  // inteface to output arbiter
  //-------------------------------------------------------------------------------------------------- 

  // logical commands 
  output logic          dec_pre_all       ;   
  output logic          dec_refr          ;   
  output logic          dec_pre           ;   
  output logic          dec_act           ;   
  output logic          dec_read          ;   
  output logic          dec_write         ;   
  // logical commands en
  input  wire          dec_pre_all_enable ;
  input  wire          dec_refr_enable    ;
  input  wire          dec_pre_enable     ;
  input  wire          dec_act_enable     ;
  input  wire          dec_read_enable    ;
  input  wire          dec_write_enable   ;
  // addititional signal                  
  output logic         dec_locked         ;     
  output logic         dec_last           ;     
  // control path                         
  output rowa_t        dec_rowa           ;     
  output cola_t        dec_cola           ;     
  output ba_t          dec_ba             ;     
  output chid_t        dec_chid           ;     
  //                                      
  output sdram_burst_t dec_burst          ; 

  //-------------------------------------------------------------------------------------------------- 
  //
  //-------------------------------------------------------------------------------------------------- 

  localparam int cTrp_m1  = cTrp  - 1;
  localparam int cTrcd_m1 = cTrcd - 1; 

  typedef enum {
    STATE_RESET_BIT   ,   // need for create simple true ready condition 
    STATE_IDLE_BIT    , 
    STATE_DECODE_BIT  , 
    STATE_PRE_BIT     , 
    STATE_TRP_BIT     , 
    STATE_ACT_BIT     , 
    STATE_TRCD_BIT    ,
    STATE_RW_BIT      , 
    STATE_ADDR_INC_BIT, 
    STATE_PRE_ALL_BIT , 
    STATE_REFR_BIT      
    } state_bits_e;

  //-------------------------------------------------------------------------------------------------- 
  //
  //-------------------------------------------------------------------------------------------------- 

  enum bit [10:0] {
    STATE_RESET     = (11'h1 << STATE_RESET_BIT)     , 
    STATE_IDLE      = (11'h1 << STATE_IDLE_BIT)      , 
    STATE_DECODE    = (11'h1 << STATE_DECODE_BIT)    , 
    STATE_PRE       = (11'h1 << STATE_PRE_BIT)       , 
    STATE_TRP       = (11'h1 << STATE_TRP_BIT)       , 
    STATE_ACT       = (11'h1 << STATE_ACT_BIT)       , 
    STATE_TRCD      = (11'h1 << STATE_TRCD_BIT)      , 
    STATE_RW        = (11'h1 << STATE_RW_BIT)        , 
    STATE_ADDR_INC  = (11'h1 << STATE_ADDR_INC_BIT)  , 
    STATE_PRE_ALL   = (11'h1 << STATE_PRE_ALL_BIT)   ,
    STATE_REFR      = (11'h1 << STATE_REFR_BIT)
    } state, next_state;

  logic   refr_mode       ; 
  logic   write_mode      ; 

  logic   burst_done      ; 
  logic   early_burst_done;

  cola_t  cola_latched  ;
  rowa_t  rowa_latched  ;
  ba_t    ba_latched    ;  
  chid_t  chid_latched  ;

  logic [3:0] burst_latched   ;
  logic [3:0] burst_shift_cnt ;

  logic [3:0] available_burst ; 

  logic [3:0] remained_burst      ; 
  logic [1:0] remained_burst_high ;
  logic [1:0] remained_burst_low  ;
  logic [1:0] remained_burst_low_latched;

  logic [3:0] last_used_burst; 
    
  wire trp_cnt_done; 
  wire trcd_cnt_done; 

  //-------------------------------------------------------------------------------------------------- 
  // use shift register instead of counter for trp time count 
  //-------------------------------------------------------------------------------------------------- 

  generate
    if (cTrp_m1 <= 1) begin : no_trp_cnt_generate 

      assign trp_cnt_done = 1'b1; 

    end 
    else begin : trp_cnt_generate 

      logic [cTrp_m1-2:0] trp_cnt;

      always_ff @(posedge clk) begin
        if (state [STATE_TRP_BIT])
          trp_cnt <= (trp_cnt << 1) | 1'b1; 
        else 
          trp_cnt <= '0;
      end 

      assign trp_cnt_done = trp_cnt [cTrp_m1-2]; 

    end 
  endgenerate 

  //-------------------------------------------------------------------------------------------------- 
  // use shift register instead of counter for trcd time count 
  //-------------------------------------------------------------------------------------------------- 

  generate
    if (cTrcd_m1 <= 1) begin : no_trcd_cnt_generate

      assign trcd_cnt_done = 1'b1;

    end 
    else begin : trcd_cnt_generate

      logic [cTrcd_m1-2:0] trcd_cnt; 

      always_ff @(posedge clk) begin 
        if (state [STATE_TRCD_BIT])
          trcd_cnt <= (trcd_cnt << 1) | 1'b1; 
        else 
          trcd_cnt <= '0;
      end 

      assign trcd_cnt_done = trcd_cnt [cTrcd_m1-2];

    end 
  endgenerate

  //-------------------------------------------------------------------------------------------------- 
  //