hssdrc_top.v

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv

    .dec0_locked        (dec0___locked        ),
    .dec0_last          (dec0___last          ),
    .dec0_rowa          (dec0___rowa          ),
    .dec0_cola          (dec0___cola          ),
    .dec0_ba            (dec0___ba            ),
    .dec0_chid          (dec0___chid          ),
    .dec0_burst         (dec0___burst         ),
    //
    .dec1_pre_all       (dec1___pre_all       ),
    .dec1_refr          (dec1___refr          ),
    .dec1_pre           (dec1___pre           ),
    .dec1_act           (dec1___act           ),
    .dec1_read          (dec1___read          ),
    .dec1_write         (dec1___write         ),
    .dec1_pre_all_enable(dec1___pre_all_enable),
    .dec1_refr_enable   (dec1___refr_enable   ),
    .dec1_pre_enable    (dec1___pre_enable    ),
    .dec1_act_enable    (dec1___act_enable    ),
    .dec1_read_enable   (dec1___read_enable   ),
    .dec1_write_enable  (dec1___write_enable  ),
    .dec1_locked        (dec1___locked        ),
    .dec1_last          (dec1___last          ),
    .dec1_rowa          (dec1___rowa          ),
    .dec1_cola          (dec1___cola          ),
    .dec1_ba            (dec1___ba            ),
    .dec1_chid          (dec1___chid          ),
    .dec1_burst         (dec1___burst         ),
    //
    .dec2_pre_all       (dec2___pre_all       ),
    .dec2_refr          (dec2___refr          ),
    .dec2_pre           (dec2___pre           ),
    .dec2_act           (dec2___act           ),
    .dec2_read          (dec2___read          ),
    .dec2_write         (dec2___write         ),
    .dec2_pre_all_enable(dec2___pre_all_enable),
    .dec2_refr_enable   (dec2___refr_enable   ),
    .dec2_pre_enable    (dec2___pre_enable    ),
    .dec2_act_enable    (dec2___act_enable    ),
    .dec2_read_enable   (dec2___read_enable   ),
    .dec2_write_enable  (dec2___write_enable  ),
    .dec2_locked        (dec2___locked        ),
    .dec2_last          (dec2___last          ),
    .dec2_rowa          (dec2___rowa          ),
    .dec2_cola          (dec2___cola          ),
    .dec2_ba            (dec2___ba            ),
    .dec2_chid          (dec2___chid          ),
    .dec2_burst         (dec2___burst         ),
    //
    .am_pre_all_enable  (access_manager___pre_all_enable),
    .am_refr_enable     (access_manager___refr_enable   ),
    .am_pre_enable      (access_manager___pre_enable    ),
    .am_act_enable      (access_manager___act_enable    ),
    .am_read_enable     (access_manager___read_enable   ),
    .am_write_enable    (access_manager___write_enable  ),
    //
    .arb_pre_all        (arbiter_out___pre_all),        
    .arb_refr           (arbiter_out___refr   ),
    .arb_pre            (arbiter_out___pre    ),
    .arb_act            (arbiter_out___act    ),
    .arb_read           (arbiter_out___read   ),
    .arb_write          (arbiter_out___write  ),
    .arb_rowa           (arbiter_out___rowa   ),
    .arb_cola           (arbiter_out___cola   ),
    .arb_ba             (arbiter_out___ba     ),
    .arb_chid           (arbiter_out___chid   ),
    .arb_burst          (arbiter_out___burst  )
  );
  //--------------------------------------------------------------------------------------------------
  //
  //-------------------------------------------------------------------------------------------------- 
  hssdrc_access_manager access_manager (
    .clk               (clk  ),  
    .reset             (reset),
    .sclr              (hssdrc_sclr),    // use internal sclr becouse there is access "fsm's"
    //
    .arb_pre_all       (arbiter_out___pre_all), 
    .arb_refr          (arbiter_out___refr   ),
    .arb_pre           (arbiter_out___pre    ),
    .arb_act           (arbiter_out___act    ),
    .arb_read          (arbiter_out___read   ),
    .arb_write         (arbiter_out___write  ),
    .arb_ba            (arbiter_out___ba     ),
    .arb_burst         (arbiter_out___burst  ),
    //
    .am_pre_all_enable (access_manager___pre_all_enable),
    .am_refr_enable    (access_manager___refr_enable   ),
    .am_pre_enable     (access_manager___pre_enable    ),
    .am_act_enable     (access_manager___act_enable    ),
    .am_read_enable    (access_manager___read_enable   ),
    .am_write_enable   (access_manager___write_enable  )   
  ); 
  //--------------------------------------------------------------------------------------------------
  //
  //-------------------------------------------------------------------------------------------------- 
  hssdrc_init_state init_state(
    .clk        (clk  ),  
    .reset      (reset),
    .sclr       (sclr ), // use external sclr becouse this is initial start fsm 
    .init_done  (init_done),  
    .pre_all    (init_state___pre_all),
    .refr       (init_state___refr   ),
    .lmr        (init_state___lmr    ),
    .rowa       (init_state___rowa   ) 
  );
  //--------------------------------------------------------------------------------------------------
  //
  //-------------------------------------------------------------------------------------------------- 
  hssdrc_mux mux (
    .init_done          (init_done), 
    //
    .init_state_pre_all (init_state___pre_all),
    .init_state_refr    (init_state___refr   ),
    .init_state_lmr     (init_state___lmr    ),
    .init_state_rowa    (init_state___rowa   ),
    //                  
    .arb_pre_all        (arbiter_out___pre_all),
    .arb_refr           (arbiter_out___refr   ),
    .arb_pre            (arbiter_out___pre    ),
    .arb_act            (arbiter_out___act    ),
    .arb_read           (arbiter_out___read   ),
    .arb_write          (arbiter_out___write  ),
    .arb_rowa           (arbiter_out___rowa   ),
    .arb_cola           (arbiter_out___cola   ),
    .arb_ba             (arbiter_out___ba     ),
    .arb_chid           (arbiter_out___chid   ),
    .arb_burst          (arbiter_out___burst  ),
    //                  
    .mux_pre_all        (mux___pre_all),
    .mux_refr           (mux___refr   ),
    .mux_pre            (mux___pre    ),
    .mux_act            (mux___act    ),
    .mux_read           (mux___read   ),
    .mux_write          (mux___write  ),
    .mux_lmr            (mux___lmr    ),
    .mux_rowa           (mux___rowa   ),
    .mux_cola           (mux___cola   ),
    .mux_ba             (mux___ba     ),
    .mux_chid           (mux___chid   ),
    .mux_burst          (mux___burst  ) 
  );
  //--------------------------------------------------------------------------------------------------
  //
  //-------------------------------------------------------------------------------------------------- 
  `ifndef HSSDRC_DQ_PIPELINE

    hssdrc_data_path data_path (
      .clk           (clk  ),
      .reset         (reset),
      .sclr          (sclr ),  // use external sclr becouse there is no any fsm
      //
      .sys_wdata     (sys_wdata    ),
      .sys_wdatam    (sys_wdatam   ),
      .sys_use_wdata (sys_use_wdata),
      .sys_vld_rdata (sys_vld_rdata), 
      .sys_chid_o    (sys_chid_o   ),
      .sys_rdata     (sys_rdata    ),
      //             
      .arb_read      (mux___read   ),
      .arb_write     (mux___write  ),
      .arb_chid      (mux___chid   ),
      .arb_burst     (mux___burst  ),
      //
      .dq            (dq   ),
      .dqm           (dqm  )
    );

  `else 

    hssdrc_data_path_p1 data_path_p1 (
      .clk           (clk  ),
      .reset         (reset),
      .sclr          (sclr ),  // use external sclr becouse there is no any fsm
      //
      .sys_wdata     (sys_wdata    ),
      .sys_wdatam    (sys_wdatam   ),
      .sys_use_wdata (sys_use_wdata),
      .sys_vld_rdata (sys_vld_rdata), 
      .sys_chid_o    (sys_chid_o   ),
      .sys_rdata     (sys_rdata    ),
      //             
      .arb_read      (mux___read   ),
      .arb_write     (mux___write  ),
      .arb_chid      (mux___chid   ),
      .arb_burst     (mux___burst  ),
      //
      .dq            (dq   ),
      .dqm           (dqm  )
    );

  `endif 
  //--------------------------------------------------------------------------------------------------
  //
  //-------------------------------------------------------------------------------------------------- 
  `ifndef HSSDRC_DQ_PIPELINE

    hssdrc_addr_path addr_path(
      .clk         (clk  ),
      .reset       (reset),
      .sclr        (sclr ),  // use external sclr becouse there is no any fsm 
      //
      .arb_pre_all (mux___pre_all), 
      .arb_refr    (mux___refr   ), 
      .arb_pre     (mux___pre    ), 
      .arb_act     (mux___act    ), 
      .arb_read    (mux___read   ), 
      .arb_write   (mux___write  ), 
      .arb_lmr     (mux___lmr    ), 
      .arb_rowa    (mux___rowa   ), 
      .arb_cola    (mux___cola   ), 
      .arb_ba      (mux___ba     ), 
      //
      .addr        (addr ),
      .ba          (ba   ),
      .cke         (cke  ),
      .cs_n        (cs_n ),
      .ras_n       (ras_n),
      .cas_n       (cas_n),
      .we_n        (we_n )
    );

  `else 

    hssdrc_addr_path_p1 addr_path_p1(
      .clk         (clk  ),
      .reset       (reset),
      .sclr        (sclr ),  // use external sclr becouse there is no any fsm 
      //
      .arb_pre_all (mux___pre_all), 
      .arb_refr    (mux___refr   ), 
      .arb_pre     (mux___pre    ), 
      .arb_act     (mux___act    ), 
      .arb_read    (mux___read   ), 
      .arb_write   (mux___write  ), 
      .arb_lmr     (mux___lmr    ), 
      .arb_rowa    (mux___rowa   ), 
      .arb_cola    (mux___cola   ), 
      .arb_ba      (mux___ba     ), 
      //
      .addr        (addr ),
      .ba          (ba   ),
      .cke         (cke  ),
      .cs_n        (cs_n ),
      .ras_n       (ras_n),
      .cas_n       (cas_n),
      .we_n        (we_n )
    );

  `endif 

endmodule