hssdrc_top.v

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv

  wire          arbiter_out___refr    ;
  wire          arbiter_out___pre     ;
  wire          arbiter_out___act     ;
  wire          arbiter_out___read    ;
  wire          arbiter_out___write   ;
  rowa_t        arbiter_out___rowa    ;
  cola_t        arbiter_out___cola    ;
  ba_t          arbiter_out___ba      ;
  chid_t        arbiter_out___chid    ;
  sdram_burst_t arbiter_out___burst   ;

  //--------------------------------------------------------------------------------------------------
  // init_state -> multiplexer
  //--------------------------------------------------------------------------------------------------

  wire    init_state___pre_all ;    
  wire    init_state___refr    ;   
  wire    init_state___lmr     ;   
  rowa_t  init_state___rowa    ;
  
  //--------------------------------------------------------------------------------------------------
  // multiplexer -> sdram_addr_path/sdram_data_path
  //--------------------------------------------------------------------------------------------------

  wire          mux___pre_all  ;           
  wire          mux___refr     ;         
  wire          mux___pre      ;         
  wire          mux___act      ;         
  wire          mux___read     ;         
  wire          mux___write    ;         
  wire          mux___lmr      ;         
  rowa_t        mux___rowa     ;         
  cola_t        mux___cola     ;         
  ba_t          mux___ba       ;         
  chid_t        mux___chid     ;         
  sdram_burst_t mux___burst    ;
  
  //
  // this clear use to disable fsm that must be off when sdram chip is not configured 
  //

  assign hssdrc_sclr = sclr | ~init_done;

  //--------------------------------------------------------------------------------------------------
  //
  //-------------------------------------------------------------------------------------------------- 

  hssdrc_refr_counter refr_cnt(
    .clk      (clk  ),  
    .reset    (reset),
    .sclr     (hssdrc_sclr ), // use internal sclr becouse there is refresh "fsm"
    .ack      (refr_cnt___ack    ),
    .hi_req   (refr_cnt___hi_req ),
    .low_req  (refr_cnt___low_req)
    ); 
  //--------------------------------------------------------------------------------------------------
  //
  //-------------------------------------------------------------------------------------------------- 
  hssdrc_arbiter_in arbiter_in ( 
    .clk              (clk  ),  
    .reset            (reset),
    .sclr             (hssdrc_sclr ), // use internal sclr becouse there is arbiter fsm                  
    //
    .sys_write        (sys_write ) , 
    .sys_read         (sys_read  ) , 
    .sys_refr         (sys_refr  ) , 
    .sys_rowa         (sys_rowa  ) , 
    .sys_cola         (sys_cola  ) , 
    .sys_ba           (sys_ba    ) , 
    .sys_burst        (sys_burst ) , 
    .sys_chid_i       (sys_chid_i) , 
    .sys_ready        (sys_ready ) , 
    //
    .refr_cnt_ack     (refr_cnt___ack    ), 
    .refr_cnt_hi_req  (refr_cnt___hi_req ), 
    .refr_cnt_low_req (refr_cnt___low_req), 
    //
    .dec0_write       (arbiter_in0___write),
    .dec0_read        (arbiter_in0___read ),
    .dec0_refr        (arbiter_in0___refr ),
    .dec0_rowa        (arbiter_in0___rowa ),
    .dec0_cola        (arbiter_in0___cola ),
    .dec0_ba          (arbiter_in0___ba   ),
    .dec0_burst       (arbiter_in0___burst),
    .dec0_chid        (arbiter_in0___chid ),
    .dec0_ready       (arbiter_in0___ready),
    //
    .dec1_write       (arbiter_in1___write),
    .dec1_read        (arbiter_in1___read ),
    .dec1_refr        (arbiter_in1___refr ),
    .dec1_rowa        (arbiter_in1___rowa ),
    .dec1_cola        (arbiter_in1___cola ),
    .dec1_ba          (arbiter_in1___ba   ),
    .dec1_burst       (arbiter_in1___burst),
    .dec1_chid        (arbiter_in1___chid ),
    .dec1_ready       (arbiter_in1___ready),
    //
    .dec2_write       (arbiter_in2___write),
    .dec2_read        (arbiter_in2___read ),
    .dec2_refr        (arbiter_in2___refr ),
    .dec2_rowa        (arbiter_in2___rowa ),
    .dec2_cola        (arbiter_in2___cola ),
    .dec2_ba          (arbiter_in2___ba   ),
    .dec2_burst       (arbiter_in2___burst),
    .dec2_chid        (arbiter_in2___chid ),
    .dec2_ready       (arbiter_in2___ready) 
  );  
  //--------------------------------------------------------------------------------------------------
  //
  //-------------------------------------------------------------------------------------------------- 
  hssdrc_ba_map ba_map (
    .clk        (clk  ),  
    .reset      (reset),
    .sclr       (hssdrc_sclr), // use internal sclr becouse there is bank access map
    //
    .update     (ba_map___update),
    .clear      (ba_map___clear ),
    .ba         (ba_map___ba    ),
    .rowa       (ba_map___rowa  ),
    //
    .pre_act_rw (ba_map___pre_act_rw),
    .act_rw     (ba_map___act_rw    ),
    .rw         (ba_map___rw        ),
    .all_close  (ba_map___all_close ) 
    );
  //--------------------------------------------------------------------------------------------------
  //
  //-------------------------------------------------------------------------------------------------- 
  hssdrc_decoder decoder (
    .clk                (clk  ),  
    .reset              (reset),
    .sclr               (hssdrc_sclr), // use internal sclr becouse there is decoders fsm
    //  
    .ba_map_update      (ba_map___update    ),
    .ba_map_clear       (ba_map___clear     ),
    .ba_map_ba          (ba_map___ba        ),
    .ba_map_rowa        (ba_map___rowa      ),
    //
    .ba_map_pre_act_rw  (ba_map___pre_act_rw),
    .ba_map_act_rw      (ba_map___act_rw    ),
    .ba_map_rw          (ba_map___rw        ),
    .ba_map_all_close   (ba_map___all_close ),
    //  
    .arb0_write         (arbiter_in0___write),
    .arb0_read          (arbiter_in0___read ),
    .arb0_refr          (arbiter_in0___refr ),
    .arb0_rowa          (arbiter_in0___rowa ),
    .arb0_cola          (arbiter_in0___cola ),
    .arb0_ba            (arbiter_in0___ba   ),
    .arb0_burst         (arbiter_in0___burst),
    .arb0_chid          (arbiter_in0___chid ),
    .arb0_ready         (arbiter_in0___ready),
    //                  
    .arb1_write         (arbiter_in1___write),
    .arb1_read          (arbiter_in1___read ),
    .arb1_refr          (arbiter_in1___refr ),
    .arb1_rowa          (arbiter_in1___rowa ),
    .arb1_cola          (arbiter_in1___cola ),
    .arb1_ba            (arbiter_in1___ba   ),
    .arb1_burst         (arbiter_in1___burst),
    .arb1_chid          (arbiter_in1___chid ),
    .arb1_ready         (arbiter_in1___ready),
    //                  
    .arb2_write         (arbiter_in2___write),
    .arb2_read          (arbiter_in2___read ),
    .arb2_refr          (arbiter_in2___refr ),
    .arb2_rowa          (arbiter_in2___rowa ),
    .arb2_cola          (arbiter_in2___cola ),
    .arb2_ba            (arbiter_in2___ba   ),
    .arb2_burst         (arbiter_in2___burst),
    .arb2_chid          (arbiter_in2___chid ),
    .arb2_ready         (arbiter_in2___ready),
    //
    .dec0_pre_all       (dec0___pre_all       ),
    .dec0_refr          (dec0___refr          ),
    .dec0_pre           (dec0___pre           ),
    .dec0_act           (dec0___act           ),
    .dec0_read          (dec0___read          ),
    .dec0_write         (dec0___write         ),
    .dec0_pre_all_enable(dec0___pre_all_enable),
    .dec0_refr_enable   (dec0___refr_enable   ),
    .dec0_pre_enable    (dec0___pre_enable    ),
    .dec0_act_enable    (dec0___act_enable    ),
    .dec0_read_enable   (dec0___read_enable   ),
    .dec0_write_enable  (dec0___write_enable  ),
    .dec0_locked        (dec0___locked        ),
    .dec0_last          (dec0___last          ),
    .dec0_rowa          (dec0___rowa          ),
    .dec0_cola          (dec0___cola          ),
    .dec0_ba            (dec0___ba            ),
    .dec0_chid          (dec0___chid          ),
    .dec0_burst         (dec0___burst         ),
    //
    .dec1_pre_all       (dec1___pre_all       ),
    .dec1_refr          (dec1___refr          ),
    .dec1_pre           (dec1___pre           ),
    .dec1_act           (dec1___act           ),
    .dec1_read          (dec1___read          ),
    .dec1_write         (dec1___write         ),
    .dec1_pre_all_enable(dec1___pre_all_enable),
    .dec1_refr_enable   (dec1___refr_enable   ),
    .dec1_pre_enable    (dec1___pre_enable    ),
    .dec1_act_enable    (dec1___act_enable    ),
    .dec1_read_enable   (dec1___read_enable   ),
    .dec1_write_enable  (dec1___write_enable  ),
    .dec1_locked        (dec1___locked        ),
    .dec1_last          (dec1___last          ),
    .dec1_rowa          (dec1___rowa          ),
    .dec1_cola          (dec1___cola          ),
    .dec1_ba            (dec1___ba            ),
    .dec1_chid          (dec1___chid          ),
    .dec1_burst         (dec1___burst         ),
    //
    .dec2_pre_all       (dec2___pre_all       ),
    .dec2_refr          (dec2___refr          ),
    .dec2_pre           (dec2___pre           ),
    .dec2_act           (dec2___act           ),
    .dec2_read          (dec2___read          ),
    .dec2_write         (dec2___write         ),
    .dec2_pre_all_enable(dec2___pre_all_enable),
    .dec2_refr_enable   (dec2___refr_enable   ),
    .dec2_pre_enable    (dec2___pre_enable    ),
    .dec2_act_enable    (dec2___act_enable    ),
    .dec2_read_enable   (dec2___read_enable   ),
    .dec2_write_enable  (dec2___write_enable  ),
    .dec2_locked        (dec2___locked        ),
    .dec2_last          (dec2___last          ),
    .dec2_rowa          (dec2___rowa          ),
    .dec2_cola          (dec2___cola          ),
    .dec2_ba            (dec2___ba            ),
    .dec2_chid          (dec2___chid          ),
    .dec2_burst         (dec2___burst         )                       
    ); 
  //--------------------------------------------------------------------------------------------------
  //
  //-------------------------------------------------------------------------------------------------- 
  hssdrc_arbiter_out arbiter_out(
    .clk                (clk), 
    .reset              (reset), 
    .sclr               (hssdrc_sclr), // use internal sclr becouse there is arbiter fsm
    //
    .dec0_pre_all       (dec0___pre_all       ),
    .dec0_refr          (dec0___refr          ),
    .dec0_pre           (dec0___pre           ),
    .dec0_act           (dec0___act           ),
    .dec0_read          (dec0___read          ),
    .dec0_write         (dec0___write         ),
    .dec0_pre_all_enable(dec0___pre_all_enable),
    .dec0_refr_enable   (dec0___refr_enable   ),
    .dec0_pre_enable    (dec0___pre_enable    ),
    .dec0_act_enable    (dec0___act_enable    ),
    .dec0_read_enable   (dec0___read_enable   ),
    .dec0_write_enable  (dec0___write_enable  ),