hssdrc_top.v

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv

//
// Project      : High-Speed SDRAM Controller with adaptive bank management and command pipeline
// 
// Project Nick : HSSDRC
// 
// Version      : 1.0-beta 
//  
// Revision     : $Revision: 1.1 $ 
// 
// Date         : $Date: 2008-03-06 13:52:43 $ 
// 
// Workfile     : hssdrc_top.v
// 
// Description  : top level of memory controller
// 
// HSSDRC is licensed under MIT License
// 
// Copyright (c) 2007-2008, Denis V.Shekhalev ([e-mail]) 
// 
// Permission  is hereby granted, free of charge, to any person obtaining a copy of
// this  software  and  associated documentation files (the "Software"), to deal in
// the  Software  without  restriction,  including without limitation the rights to
// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
// the  Software, and to permit persons to whom the Software is furnished to do so,
// subject to the following conditions:
// 
// The  above  copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
// 
// THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
// FOR  A  PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
// COPYRIGHT  HOLDERS  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
// IN  AN  ACTION  OF  CONTRACT,  TORT  OR  OTHERWISE,  ARISING  FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//


`include "hssdrc_timescale.vh"

`include "hssdrc_define.vh"

module hssdrc_top (
  clk           , 
  reset         , 
  sclr          , 
  sys_write     ,
  sys_read      ,
  sys_refr      ,
  sys_rowa      ,
  sys_cola      ,
  sys_ba        ,
  sys_burst     ,
  sys_chid_i    ,
  sys_wdata     ,
  sys_wdatam    ,  
  sys_ready     ,
  sys_use_wdata , 
  sys_vld_rdata ,
  sys_chid_o    ,
  sys_rdata     ,
  dq            , 
  dqm           , 
  addr          , 
  ba            , 
  cke           , 
  cs_n          , 
  ras_n         , 
  cas_n         , 
  we_n          
  );

  input wire clk  ;
  input wire reset;
  input wire sclr ;

  //--------------------------------------------------------------------------------------------------
  // system interface 
  //-------------------------------------------------------------------------------------------------- 

  input  wire    sys_write     ;      
  input  wire    sys_read      ;     
  input  wire    sys_refr      ;     
  input  rowa_t  sys_rowa      ;     
  input  cola_t  sys_cola      ;     
  input  ba_t    sys_ba        ;     
  input  burst_t sys_burst     ;     
  input  chid_t  sys_chid_i    ;     
  input  data_t  sys_wdata     ;     
  input  datam_t sys_wdatam    ;    
   
  output logic   sys_ready     ; 
  output logic   sys_use_wdata ; 
  output logic   sys_vld_rdata ; 
  output chid_t  sys_chid_o    ; 
  output data_t  sys_rdata     ;

  //--------------------------------------------------------------------------------------------------
  // sdram interface 
  //--------------------------------------------------------------------------------------------------  

  inout   wire [pDataBits-1:0] dq;
  output  datam_t       dqm;  
  output  sdram_addr_t  addr;
  output  ba_t          ba; 
  output  logic         cke;
  output  logic         cs_n;
  output  logic         ras_n;
  output  logic         cas_n;
  output  logic         we_n;

  //--------------------------------------------------------------------------------------------------  
  // internal signals 
  //--------------------------------------------------------------------------------------------------

  wire init_done; 
  wire hssdrc_sclr; 

  //--------------------------------------------------------------------------------------------------
  // refr_cnt <-> arbiter_in  
  //--------------------------------------------------------------------------------------------------

  wire refr_cnt___ack     ;
  wire refr_cnt___hi_req  ;
  wire refr_cnt___low_req ;

  //--------------------------------------------------------------------------------------------------
  // arbiter_in <-> decoder's
  //--------------------------------------------------------------------------------------------------

  wire    arbiter_in0___write  ;  
  wire    arbiter_in0___read   ;
  wire    arbiter_in0___refr   ;
  rowa_t  arbiter_in0___rowa   ;
  cola_t  arbiter_in0___cola   ;
  ba_t    arbiter_in0___ba     ;
  burst_t arbiter_in0___burst  ;
  chid_t  arbiter_in0___chid   ;
  wire    arbiter_in0___ready  ;
  //                            
  wire    arbiter_in1___write  ;
  wire    arbiter_in1___read   ;
  wire    arbiter_in1___refr   ;
  rowa_t  arbiter_in1___rowa   ;
  cola_t  arbiter_in1___cola   ;
  ba_t    arbiter_in1___ba     ;
  burst_t arbiter_in1___burst  ;
  chid_t  arbiter_in1___chid   ;
  wire    arbiter_in1___ready  ;
  //                            
  wire    arbiter_in2___write  ;
  wire    arbiter_in2___read   ;
  wire    arbiter_in2___refr   ;
  rowa_t  arbiter_in2___rowa   ;
  cola_t  arbiter_in2___cola   ;
  ba_t    arbiter_in2___ba     ;
  burst_t arbiter_in2___burst  ;
  chid_t  arbiter_in2___chid   ;
  wire    arbiter_in2___ready  ;

  //--------------------------------------------------------------------------------------------------
  // ba_map <-> decoder's 
  //--------------------------------------------------------------------------------------------------

  wire    ba_map___update      ;  
  wire    ba_map___clear       ;
  ba_t    ba_map___ba          ;
  rowa_t  ba_map___rowa        ;                
  wire    ba_map___pre_act_rw  ;
  wire    ba_map___act_rw      ;
  wire    ba_map___rw          ;
  wire    ba_map___all_close   ;

  //--------------------------------------------------------------------------------------------------
  // decoder's <-> arbiter_out 
  //--------------------------------------------------------------------------------------------------

  wire          dec0___pre_all         ;
  wire          dec0___refr            ;
  wire          dec0___pre             ;
  wire          dec0___act             ;
  wire          dec0___read            ;
  wire          dec0___write           ;
  wire          dec0___pre_all_enable  ;
  wire          dec0___refr_enable     ;
  wire          dec0___pre_enable      ;
  wire          dec0___act_enable      ;
  wire          dec0___read_enable     ;
  wire          dec0___write_enable    ;
  wire          dec0___locked          ;
  wire          dec0___last            ;
  rowa_t        dec0___rowa            ;
  cola_t        dec0___cola            ;
  ba_t          dec0___ba              ;
  chid_t        dec0___chid            ;
  sdram_burst_t dec0___burst           ;
  //
  wire          dec1___pre_all         ;
  wire          dec1___refr            ;
  wire          dec1___pre             ;
  wire          dec1___act             ;
  wire          dec1___read            ;
  wire          dec1___write           ;
  wire          dec1___pre_all_enable  ;
  wire          dec1___refr_enable     ;
  wire          dec1___pre_enable      ;
  wire          dec1___act_enable      ;
  wire          dec1___read_enable     ;
  wire          dec1___write_enable    ;
  wire          dec1___locked          ;
  wire          dec1___last            ;
  rowa_t        dec1___rowa            ;
  cola_t        dec1___cola            ;
  ba_t          dec1___ba              ;
  chid_t        dec1___chid            ;
  sdram_burst_t dec1___burst           ;
  //
  wire          dec2___pre_all         ;
  wire          dec2___refr            ;
  wire          dec2___pre             ;
  wire          dec2___act             ;
  wire          dec2___read            ;
  wire          dec2___write           ;
  wire          dec2___pre_all_enable  ;
  wire          dec2___refr_enable     ;
  wire          dec2___pre_enable      ;
  wire          dec2___act_enable      ;
  wire          dec2___read_enable     ;
  wire          dec2___write_enable    ;
  wire          dec2___locked          ;
  wire          dec2___last            ;
  rowa_t        dec2___rowa            ;
  cola_t        dec2___cola            ;
  ba_t          dec2___ba              ;
  chid_t        dec2___chid            ;
  sdram_burst_t dec2___burst           ;

  //--------------------------------------------------------------------------------------------------
  // access_manager -> arbiter_out 
  //--------------------------------------------------------------------------------------------------

  wire       access_manager___pre_all_enable  ;
  wire       access_manager___refr_enable     ;
  wire [0:3] access_manager___pre_enable      ;
  wire [0:3] access_manager___act_enable      ;
  wire [0:3] access_manager___read_enable     ;
  wire [0:3] access_manager___write_enable    ;

  //--------------------------------------------------------------------------------------------------
  // arbiter_out -> multiplexer/access_manager 
  //--------------------------------------------------------------------------------------------------

  wire          arbiter_out___pre_all ;