📄 hssdrc_arbiter_out.v
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(dec1_last &
((dec1_read & dec1_read_enable ) |
( dec1_write & dec1_write_enable ))
);
assign dec2_access_done = (dec2_refr & dec2_refr_enable) |
(dec2_last &
((dec2_read & dec2_read_enable ) |
( dec2_write & dec2_write_enable ))
);
//
//
//
assign arb_ack = (dec0_access_done && (arb == ARB0)) |
(dec1_access_done && (arb == ARB1)) |
(dec2_access_done && (arb == ARB2));
//--------------------------------------------------------------------------------------------------
// decoder roundabout : dec0 -> dec1 -> dec2 -> dec0 -> dec1
//
// arbiter for command pipeline need in folow comparators :
// 0 : dec0 - dec1 -> select dec1
// : dec0 - dec2 & dec1 - dec2 -> select dec2
// 1 : dec1 - dec2 -> select dec2
// : dec1 - dec2 & dec2 - dec0 -> select dec0
// 2 : dec2 - dec0 -> select dec0
// : dec2 - dec1 & dec0 - dec1 -> select dec1
// we can reclock it. becouse "ba" and "locked" is valid 1 tick before command
//--------------------------------------------------------------------------------------------------
always_ff @(posedge clk) begin : locked_and_bank_access_comparator
dec1_can_have_access_when_arb_is_0 <= ~dec0_locked & (dec1_ba != dec0_ba);
dec2_can_have_access_when_arb_is_0 <= ~dec0_locked & (dec2_ba != dec0_ba) & ~dec1_locked & (dec2_ba != dec1_ba);
dec2_can_have_access_when_arb_is_1 <= ~dec1_locked & (dec2_ba != dec1_ba);
dec0_can_have_access_when_arb_is_1 <= ~dec1_locked & (dec0_ba != dec1_ba) & ~dec2_locked & (dec0_ba != dec2_ba);
dec0_can_have_access_when_arb_is_2 <= ~dec2_locked & (dec0_ba != dec2_ba);
dec1_can_have_access_when_arb_is_2 <= ~dec2_locked & (dec1_ba != dec2_ba) & ~dec0_locked & (dec1_ba != dec0_ba);
end
//
//
//
always_comb begin : control_path_arbiter
dec0_pre_all_enable = 1'b0;
dec0_refr_enable = 1'b0;
dec0_pre_enable = 1'b0;
dec0_act_enable = 1'b0;
dec0_read_enable = 1'b0;
dec0_write_enable = 1'b0;
dec1_pre_all_enable = 1'b0;
dec1_refr_enable = 1'b0;
dec1_pre_enable = 1'b0;
dec1_act_enable = 1'b0;
dec1_read_enable = 1'b0;
dec1_write_enable = 1'b0;
dec2_pre_all_enable = 1'b0;
dec2_refr_enable = 1'b0;
dec2_pre_enable = 1'b0;
dec2_act_enable = 1'b0;
dec2_read_enable = 1'b0;
dec2_write_enable = 1'b0;
arb_pre_all = 1'b0;
arb_refr = 1'b0;
arb_pre = 1'b0;
arb_act = 1'b0;
arb_read = 1'b0;
arb_write = 1'b0;
ba_rowa_mux = arb;
unique case (arb)
ARB0 : begin : dec0_is_master
dec0_pre_all_enable = am_pre_all_enable ;
dec0_refr_enable = am_refr_enable ;
dec0_pre_enable = am_pre_enable [dec0_ba];
dec0_act_enable = am_act_enable [dec0_ba];
dec0_read_enable = am_read_enable [dec0_ba];
dec0_write_enable = am_write_enable [dec0_ba];
arb_pre_all = dec0_pre_all & dec0_pre_all_enable ;
arb_refr = dec0_refr & dec0_refr_enable ;
arb_pre = dec0_pre & dec0_pre_enable ;
arb_act = dec0_act & dec0_act_enable ;
arb_read = dec0_read & dec0_read_enable ;
arb_write = dec0_write & dec0_write_enable ;
`ifndef HSSDRC_SHARE_NONE_DECODER
if (~dec0_access_enable) begin
if (dec1_can_have_access_when_arb_is_0) begin
ba_rowa_mux = ARB1;
//
dec1_pre_enable = am_pre_enable [dec1_ba];
arb_pre = dec1_pre & dec1_pre_enable ;
//
`ifndef HSSDRC_NOT_SHARE_ACT_COMMAND
dec1_act_enable = am_act_enable [dec1_ba];
arb_act = dec1_act & dec1_act_enable ;
`endif
end
`ifndef HSSDRC_SHARE_ONE_DECODER
if (~dec1_bank_access_enable & dec2_can_have_access_when_arb_is_0) begin
`else
else if (dec2_can_have_access_when_arb_is_0) begin
`endif
ba_rowa_mux = ARB2;
//
dec2_pre_enable = am_pre_enable [dec2_ba];
arb_pre = dec2_pre & dec2_pre_enable ;
//
`ifndef HSSDRC_NOT_SHARE_ACT_COMMAND
dec2_act_enable = am_act_enable [dec2_ba];
arb_act = dec2_act & dec2_act_enable ;
`endif
end
end
`endif // HSSDRC_SHARE_NONE_DECODER
end
ARB1 : begin : dec1_is_master
dec1_pre_all_enable = am_pre_all_enable ;
dec1_refr_enable = am_refr_enable ;
dec1_pre_enable = am_pre_enable [dec1_ba];
dec1_act_enable = am_act_enable [dec1_ba];
dec1_read_enable = am_read_enable [dec1_ba];
dec1_write_enable = am_write_enable [dec1_ba];
arb_pre_all = dec1_pre_all & dec1_pre_all_enable ;
arb_refr = dec1_refr & dec1_refr_enable ;
arb_pre = dec1_pre & dec1_pre_enable ;
arb_act = dec1_act & dec1_act_enable ;
arb_read = dec1_read & dec1_read_enable ;
arb_write = dec1_write & dec1_write_enable ;
`ifndef HSSDRC_SHARE_NONE_DECODER
if (~dec1_access_enable) begin
if (dec2_can_have_access_when_arb_is_1) begin
ba_rowa_mux = ARB2;
//
dec2_pre_enable = am_pre_enable [dec2_ba];
arb_pre = dec2_pre & dec2_pre_enable ;
//
`ifndef HSSDRC_NOT_SHARE_ACT_COMMAND
dec2_act_enable = am_act_enable [dec2_ba];
arb_act = dec2_act & dec2_act_enable ;
`endif
end
`ifndef HSSDRC_SHARE_ONE_DECODER
if (~dec2_bank_access_enable & dec0_can_have_access_when_arb_is_1) begin
`else
else if (dec0_can_have_access_when_arb_is_1) begin
`endif
ba_rowa_mux = ARB0;
//
dec0_pre_enable = am_pre_enable [dec0_ba];
arb_pre = dec0_pre & dec0_pre_enable ;
//
`ifndef HSSDRC_NOT_SHARE_ACT_COMMAND
dec0_act_enable = am_act_enable [dec0_ba];
arb_act = dec0_act & dec0_act_enable ;
`endif
end
end
`endif // HSSDRC_SHARE_NONE_DECODER
end
ARB2 : begin : dec2_is_master
dec2_pre_all_enable = am_pre_all_enable ;
dec2_refr_enable = am_refr_enable ;
dec2_pre_enable = am_pre_enable [dec2_ba] ;
dec2_act_enable = am_act_enable [dec2_ba] ;
dec2_read_enable = am_read_enable [dec2_ba] ;
dec2_write_enable = am_write_enable [dec2_ba] ;
arb_pre_all = dec2_pre_all & dec2_pre_all_enable ;
arb_refr = dec2_refr & dec2_refr_enable ;
arb_pre = dec2_pre & dec2_pre_enable ;
arb_act = dec2_act & dec2_act_enable ;
arb_read = dec2_read & dec2_read_enable ;
arb_write = dec2_write & dec2_write_enable ;
`ifndef HSSDRC_SHARE_NONE_DECODER
if (~dec2_access_enable) begin
if (dec0_can_have_access_when_arb_is_2) begin
ba_rowa_mux = ARB0;
//
dec0_pre_enable = am_pre_enable [dec0_ba];
arb_pre = dec0_pre & dec0_pre_enable ;
//
`ifndef HSSDRC_NOT_SHARE_ACT_COMMAND
dec0_act_enable = am_act_enable [dec0_ba];
arb_act = dec0_act & dec0_act_enable ;
`endif
end
`ifndef HSSDRC_SHARE_ONE_DECODER
if (~dec0_bank_access_enable & dec1_can_have_access_when_arb_is_2) begin
`else
else if (dec1_can_have_access_when_arb_is_2) begin
`endif
ba_rowa_mux = ARB1;
//
dec1_pre_enable = am_pre_enable [dec1_ba];
arb_pre = dec1_pre & dec1_pre_enable ;
//
`ifndef HSSDRC_NOT_SHARE_ACT_COMMAND
dec1_act_enable = am_act_enable [dec1_ba];
arb_act = dec1_act & dec1_act_enable ;
`endif
end
end
`endif // HSSDRC_SHARE_NONE_DECODER
end
endcase
end
always_comb begin : mux_addr_path2arbiter
//
// no complex mux : used in read/write command
//
arb_cola = dec0_cola;
arb_chid = dec0_chid;
arb_burst = dec0_burst;
unique case (arb)
ARB0 : begin
arb_cola = dec0_cola;
arb_chid = dec0_chid;
arb_burst = dec0_burst;
end
ARB1 : begin
arb_cola = dec1_cola;
arb_chid = dec1_chid;
arb_burst = dec1_burst;
end
ARB2 : begin
arb_cola = dec2_cola;
arb_chid = dec2_chid;
arb_burst = dec2_burst;
end
default : begin end
endcase
//
// complex mux used in pre command
//
arb_ba = dec0_ba;
unique case (ba_rowa_mux)
ARB0 : arb_ba = dec0_ba;
ARB1 : arb_ba = dec1_ba;
ARB2 : arb_ba = dec2_ba;
endcase
//
// complex mux used in act command
//
arb_rowa = dec0_rowa;
`ifndef HSSDRC_NOT_SHARE_ACT_COMMAND
unique case (ba_rowa_mux)
`else
unique case (arb)
`endif
ARB0 : arb_rowa = dec0_rowa;
ARB1 : arb_rowa = dec1_rowa;
ARB2 : arb_rowa = dec2_rowa;
endcase
end
endmodule
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