booth_tb.tf

一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码

module testbench();

// Inputs
    reg [15:0] A;
    reg [15:0] B;


// Outputs
    wire [31:0] P;

// Instantiate the UUT
    booth uut (.A(A), .B(B), .P(P));

initial
    $monitor($time, " A = %d  B = %d   P=", A, B, P);

initial begin
   #100 begin A = 25; B=25; end
   #100 begin A = 1; B=-200; end
   #100 begin A = 250; B=1; end
   #100 begin A = -120; B=-100; end
   #100 begin A = 125; B=0; end
   #100 begin A = -35; B=428; end
   #100 begin A = 255; B=177; end
end

//Finish the simulation at time 800
initial begin
    #800 $finish;
end
endmodule