dds.hif

一个可用的很不错的DDS 频率合成程序

Version 7.0 Build 33 02/05/2007 SJ Full Version
11
787
OFF
OFF
OFF
OFF
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
dds
# storage
db|dds.(0).cnf
db|dds.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
dds.vhd
847672ed5688ee1290a415a8ae2af180
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
SUM99
# storage
db|dds.(1).cnf
db|dds.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
dds.vhd
847672ed5688ee1290a415a8ae2af180
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(k)
9 downto 0
PARAMETER_STRING
USR
 constraint(out1)
9 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
SUM99:U0
}
# end
# entity
REG1
# storage
db|dds.(2).cnf
db|dds.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
dds.vhd
847672ed5688ee1290a415a8ae2af180
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(d)
9 downto 0
PARAMETER_STRING
USR
 constraint(q)
9 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
REG1:U1
}
# end
# entity
ROM
# storage
db|dds.(3).cnf
db|dds.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
dds.vhd
847672ed5688ee1290a415a8ae2af180
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(addr)
9 downto 0
PARAMETER_STRING
USR
 constraint(outp)
8 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
ROM:U2
}
# end
# entity
REG2
# storage
db|dds.(4).cnf
db|dds.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
dds.vhd
847672ed5688ee1290a415a8ae2af180
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(d1)
8 downto 0
PARAMETER_STRING
USR
 constraint(q)
8 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
REG2:U3
}
# end
# entity
altsyncram
# storage
db|dds.(5).cnf
db|dds.(5).cnf
# case_insensitive
# source_file
..|libraries|megafunctions|altsyncram.tdf
54ca23b6a4929c50f5115a9a53314c
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
1
PARAMETER_UNKNOWN
USR
WIDTHAD_A
10
PARAMETER_UNKNOWN
USR
NUMWORDS_A
1024
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
DDS0.rtl.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_uau
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
..|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
..|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
..|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
..|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
}
# end
# entity
altsyncram_uau
# storage
db|dds.(6).cnf
db|dds.(6).cnf
# case_insensitive
# source_file
db|altsyncram_uau.tdf
f9845cbe97749c4bb045cd3015d97d98
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
DDS0.rtl.mif
832e112e46d96ef5aa6e22c2e36ea3
}
# end
# complete