dds.fit.qmsg

一个可用的很不错的DDS 频率合成程序

{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "20 unused 3.30 11 9 0 " "Info: Number of I/O pins in group: 20 (unused VREF, 3.30 VCCIO, 11 input, 9 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 4 30 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  30 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 35 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  35 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 1 36 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  36 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 36 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  36 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.930 ns register register " "Info: Estimated most critical path is register to register delay of 9.930 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG1:U1\|Q\[8\] 1 REG LAB_X19_Y7 41 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y7; Fanout = 41; REG Node = 'REG1:U1\|Q\[8\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG1:U1|Q[8] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.335 ns) + CELL(0.529 ns) 1.864 ns ROM:U2\|Equal0~12487 2 COMB LAB_X17_Y8 16 " "Info: 2: + IC(1.335 ns) + CELL(0.529 ns) = 1.864 ns; Loc. = LAB_X17_Y8; Fanout = 16; COMB Node = 'ROM:U2\|Equal0~12487'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.864 ns" { REG1:U1|Q[8] ROM:U2|Equal0~12487 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.521 ns) + CELL(0.370 ns) 3.755 ns ROM:U2\|Equal0~12641 3 COMB LAB_X20_Y7 3 " "Info: 3: + IC(1.521 ns) + CELL(0.370 ns) = 3.755 ns; Loc. = LAB_X20_Y7; Fanout = 3; COMB Node = 'ROM:U2\|Equal0~12641'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.891 ns" { ROM:U2|Equal0~12487 ROM:U2|Equal0~12641 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.616 ns) 4.558 ns ROM:U2\|WideOr6~904 4 COMB LAB_X20_Y7 1 " "Info: 4: + IC(0.187 ns) + CELL(0.616 ns) = 4.558 ns; Loc. = LAB_X20_Y7; Fanout = 1; COMB Node = 'ROM:U2\|WideOr6~904'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.803 ns" { ROM:U2|Equal0~12641 ROM:U2|WideOr6~904 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.320 ns) + CELL(0.206 ns) 6.084 ns ROM:U2\|WideOr6~905 5 COMB LAB_X20_Y8 1 " "Info: 5: + IC(1.320 ns) + CELL(0.206 ns) = 6.084 ns; Loc. = LAB_X20_Y8; Fanout = 1; COMB Node = 'ROM:U2\|WideOr6~905'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { ROM:U2|WideOr6~904 ROM:U2|WideOr6~905 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.165 ns) + CELL(0.370 ns) 7.619 ns ROM:U2\|WideOr6~906 6 COMB LAB_X21_Y10 2 " "Info: 6: + IC(1.165 ns) + CELL(0.370 ns) = 7.619 ns; Loc. = LAB_X21_Y10; Fanout = 2; COMB Node = 'ROM:U2\|WideOr6~906'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.535 ns" { ROM:U2|WideOr6~905 ROM:U2|WideOr6~906 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 8.430 ns ROM:U2\|WideOr4~672 7 COMB LAB_X21_Y10 1 " "Info: 7: + IC(0.605 ns) + CELL(0.206 ns) = 8.430 ns; Loc. = LAB_X21_Y10; Fanout = 1; COMB Node = 'ROM:U2\|WideOr4~672'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { ROM:U2|WideOr6~906 ROM:U2|WideOr4~672 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.499 ns) 9.822 ns ROM:U2\|WideOr4~673 8 COMB LAB_X21_Y7 1 " "Info: 8: + IC(0.893 ns) + CELL(0.499 ns) = 9.822 ns; Loc. = LAB_X21_Y7; Fanout = 1; COMB Node = 'ROM:U2\|WideOr4~673'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.392 ns" { ROM:U2|WideOr4~672 ROM:U2|WideOr4~673 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.930 ns ROM:U2\|OUTP\[3\] 9 REG LAB_X21_Y7 1 " "Info: 9: + IC(0.000 ns) + CELL(0.108 ns) = 9.930 ns; Loc. = LAB_X21_Y7; Fanout = 1; REG Node = 'ROM:U2\|OUTP\[3\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { ROM:U2|WideOr4~673 ROM:U2|OUTP[3] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.904 ns ( 29.24 % ) " "Info: Total cell delay = 2.904 ns ( 29.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.026 ns ( 70.76 % ) " "Info: Total interconnect delay = 7.026 ns ( 70.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.930 ns" { REG1:U1|Q[8] ROM:U2|Equal0~12487 ROM:U2|Equal0~12641 ROM:U2|WideOr6~904 ROM:U2|WideOr6~905 ROM:U2|WideOr6~906 ROM:U2|WideOr4~672 ROM:U2|WideOr4~673 ROM:U2|OUTP[3] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}