dds.vho

一个可用的很不错的DDS 频率合成程序

SIGNAL \U2|WideOr7~1407\ : std_logic;
SIGNAL \U2|WideOr7~1408\ : std_logic;
SIGNAL \U2|WideOr7~1362\ : std_logic;
SIGNAL \U2|WideOr7~1358\ : std_logic;
SIGNAL \U2|WideOr7~1415\ : std_logic;
SIGNAL \U2|WideOr7~1412\ : std_logic;
SIGNAL \U2|Equal0~12628\ : std_logic;
SIGNAL \U2|WideOr3~473\ : std_logic;
SIGNAL \U2|WideOr3~482\ : std_logic;
SIGNAL \U2|Equal0~12627\ : std_logic;
SIGNAL \U2|WideOr4~664\ : std_logic;
SIGNAL \U2|Equal0~12676\ : std_logic;
SIGNAL \U2|Equal0~12629\ : std_logic;
SIGNAL \U2|Equal0~12647\ : std_logic;
SIGNAL \U2|Equal0~12630\ : std_logic;
SIGNAL \U2|Equal0~12538\ : std_logic;
SIGNAL \U2|WideOr4~665\ : std_logic;
SIGNAL \U2|WideOr4~666\ : std_logic;
SIGNAL \U2|WideOr4~667\ : std_logic;
SIGNAL \U2|WideOr4~668\ : std_logic;
SIGNAL \U2|WideOr4~672\ : std_logic;
SIGNAL \U2|WideOr4~673\ : std_logic;
SIGNAL \U3|Q[3]~feeder\ : std_logic;
SIGNAL \U2|Equal0~12650\ : std_logic;
SIGNAL \U2|Equal0~12646\ : std_logic;
SIGNAL \U2|Equal0~12586\ : std_logic;
SIGNAL \U2|WideOr7~1399\ : std_logic;
SIGNAL \U2|Equal0~12563\ : std_logic;
SIGNAL \U2|WideOr1~892\ : std_logic;
SIGNAL \U2|WideOr1~888\ : std_logic;
SIGNAL \U2|WideOr1~928\ : std_logic;
SIGNAL \U2|Equal0~12609\ : std_logic;
SIGNAL \U2|WideOr1~909\ : std_logic;
SIGNAL \U2|WideOr0~369\ : std_logic;
SIGNAL \U2|Equal0~12608\ : std_logic;
SIGNAL \U2|WideOr0~372\ : std_logic;
SIGNAL \U2|Equal0~12575\ : std_logic;
SIGNAL \U2|WideOr2~591\ : std_logic;
SIGNAL \U2|Equal0~12631\ : std_logic;
SIGNAL \U2|WideOr2~604\ : std_logic;
SIGNAL \U2|WideOr2~592\ : std_logic;
SIGNAL \U2|WideOr0~370\ : std_logic;
SIGNAL \U2|WideOr0~373\ : std_logic;
SIGNAL \U2|WideOr0~374\ : std_logic;
SIGNAL \U2|Equal0~12570\ : std_logic;
SIGNAL \U2|Equal0~12556\ : std_logic;
SIGNAL \U2|WideOr2~587\ : std_logic;
SIGNAL \U2|WideOr3~481\ : std_logic;
SIGNAL \U2|WideOr3~460\ : std_logic;
SIGNAL \U2|WideOr3~461\ : std_logic;
SIGNAL \U2|WideOr1~905\ : std_logic;
SIGNAL \U2|WideOr1~906\ : std_logic;
SIGNAL \U2|WideOr1~908\ : std_logic;
SIGNAL \U2|WideOr3~474\ : std_logic;
SIGNAL \U2|WideOr1~832\ : std_logic;
SIGNAL \U2|WideOr1~828\ : std_logic;
SIGNAL \U2|WideOr1~925\ : std_logic;
SIGNAL \U2|WideOr3~483\ : std_logic;
SIGNAL \U2|WideOr3~477\ : std_logic;
SIGNAL \U2|WideOr3~478\ : std_logic;
SIGNAL \U2|Equal0~12478\ : std_logic;
SIGNAL \U2|Equal0~12642\ : std_logic;
SIGNAL \U2|Equal0~12599\ : std_logic;
SIGNAL \U2|Equal0~12648\ : std_logic;
SIGNAL \U2|WideOr3~465\ : std_logic;
SIGNAL \U2|WideOr3~466\ : std_logic;
SIGNAL \U2|WideOr3~475\ : std_logic;
SIGNAL \U2|WideOr3~476\ : std_logic;
SIGNAL \U2|WideOr3~479\ : std_logic;
SIGNAL \U2|WideOr3~480\ : std_logic;
SIGNAL \U2|Equal0~12507\ : std_logic;
SIGNAL \U2|WideOr2~584\ : std_logic;
SIGNAL \U2|Equal0~12587\ : std_logic;
SIGNAL \U2|WideOr2~596\ : std_logic;
SIGNAL \U2|Equal0~12675\ : std_logic;
SIGNAL \U2|Equal0~12604\ : std_logic;
SIGNAL \U2|WideOr2~600\ : std_logic;
SIGNAL \U2|WideOr2~601\ : std_logic;
SIGNAL \U2|Equal0~12613\ : std_logic;
SIGNAL \U2|WideOr2~597\ : std_logic;
SIGNAL \U2|Equal0~12594\ : std_logic;
SIGNAL \U2|WideOr2~598\ : std_logic;
SIGNAL \U2|WideOr2~599\ : std_logic;
SIGNAL \U2|WideOr2~602\ : std_logic;
SIGNAL \U2|WideOr1~929\ : std_logic;
SIGNAL \U2|WideOr1~930\ : std_logic;
SIGNAL \U2|WideOr1~873\ : std_logic;
SIGNAL \U2|WideOr1~927\ : std_logic;
SIGNAL \U2|WideOr1~912\ : std_logic;
SIGNAL \U2|WideOr1~913\ : std_logic;
SIGNAL \U2|Equal0~12644\ : std_logic;
SIGNAL \U2|Equal0~12610\ : std_logic;
SIGNAL \U2|Equal0~12652\ : std_logic;
SIGNAL \U2|WideOr1~911\ : std_logic;
SIGNAL \U2|WideOr1~914\ : std_logic;
SIGNAL \U2|WideOr1~926\ : std_logic;
SIGNAL \U2|WideOr1~915\ : std_logic;
SIGNAL \U2|WideOr2~594\ : std_logic;
SIGNAL \U2|WideOr2~603\ : std_logic;
SIGNAL \U3|Q[5]~feeder\ : std_logic;
SIGNAL \U2|WideOr1~921\ : std_logic;
SIGNAL \U2|WideOr1~922\ : std_logic;
SIGNAL \U2|Equal0~12484\ : std_logic;
SIGNAL \U2|WideOr1~923\ : std_logic;
SIGNAL \U2|Equal0~12535\ : std_logic;
SIGNAL \U2|Equal0~12663\ : std_logic;
SIGNAL \U2|Equal0~12669\ : std_logic;
SIGNAL \U2|WideOr1~919\ : std_logic;
SIGNAL \U2|WideOr1~920\ : std_logic;
SIGNAL \U2|WideOr1~924\ : std_logic;
SIGNAL \U2|WideOr1~916\ : std_logic;
SIGNAL \U2|WideOr1\ : std_logic;
SIGNAL \U3|Q[6]~feeder\ : std_logic;
SIGNAL \U2|WideOr2~562\ : std_logic;
SIGNAL \U2|WideOr2~559\ : std_logic;
SIGNAL \U2|WideOr2~605\ : std_logic;
SIGNAL \U2|WideOr0~377\ : std_logic;
SIGNAL \U2|WideOr0~378\ : std_logic;
SIGNAL \U2|WideOr0~350\ : std_logic;
SIGNAL \U2|WideOr0~376\ : std_logic;
SIGNAL \U2|WideOr0\ : std_logic;
SIGNAL \U3|Q\ : std_logic_vector(8 DOWNTO 0);
SIGNAL \U2|OUTP\ : std_logic_vector(8 DOWNTO 0);
SIGNAL \U1|Q\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U0|TEMP\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \K~combout\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|WideNor0_rtl_0|auto_generated|q_a\ : std_logic_vector(0 DOWNTO 0);

BEGIN

ww_K <= K;
ww_EN <= EN;
ww_RESET <= RESET;
ww_CLK <= CLK;
Q <= ww_Q;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\U2|WideNor0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\U0|TEMP\(0) & \U0|TEMP\(1) & \U0|TEMP\(2) & \U0|TEMP\(3) & \U0|TEMP\(4) & \U0|TEMP\(5) & \U0|TEMP\(6) & \U0|TEMP\(7) & \U0|TEMP\(8) & \U0|TEMP\(9));

\U2|WideNor0_rtl_0|auto_generated|q_a\(0) <= \U2|WideNor0_rtl_0|auto_generated|ram_block1a0_PORTADATAOUT_bus\(0);

\RESET~clkctrl_I_INCLK_bus\ <= (gnd & gnd & gnd & \RESET~combout\);

\CLK~clkctrl_I_INCLK_bus\ <= (gnd & gnd & gnd & \CLK~combout\);

\U2|Equal0~12474_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|Equal0~12474\ = \U2|Equal0~12473\ & \U2|Equal0~12468\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \U2|Equal0~12473\,
	datad => \U2|Equal0~12468\,
	combout => \U2|Equal0~12474\);

\U2|WideOr3~454_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|WideOr3~454\ = \U2|Equal0~12475\ & !\U2|Equal0~12477\ & (!\U2|Equal0~12472\ # !\U2|Equal0~12474\) # !\U2|Equal0~12475\ & (!\U2|Equal0~12472\ # !\U2|Equal0~12474\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001010100111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \U2|Equal0~12475\,
	datab => \U2|Equal0~12474\,
	datac => \U2|Equal0~12472\,
	datad => \U2|Equal0~12477\,
	combout => \U2|WideOr3~454\);

\U2|Equal0~12483_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|Equal0~12483\ = \U1|Q\(1) & !\U1|Q\(2) & \U1|Q\(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \U1|Q\(1),
	datac => \U1|Q\(2),
	datad => \U1|Q\(3),
	combout => \U2|Equal0~12483\);

\U2|WideOr3~455_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|WideOr3~455\ = \U2|WideOr3~454\ & !\U2|Equal0~12484\ & (!\U2|Equal0~12632\ # !\U2|Equal0~12478\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \U2|WideOr3~454\,
	datab => \U2|Equal0~12478\,
	datac => \U2|Equal0~12484\,
	datad => \U2|Equal0~12632\,
	combout => \U2|WideOr3~455\);

\U2|Equal0~12501_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|Equal0~12501\ = \U2|Equal0~12490\ & \U1|Q\(3) & \U2|Equal0~12500\ & !\U1|Q\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \U2|Equal0~12490\,
	datab => \U1|Q\(3),
	datac => \U2|Equal0~12500\,
	datad => \U1|Q\(0),
	combout => \U2|Equal0~12501\);

\U2|Equal0~12504_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|Equal0~12504\ = \U2|Equal0~12502\ & \U2|Equal0~12503\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \U2|Equal0~12502\,
	datad => \U2|Equal0~12503\,
	combout => \U2|Equal0~12504\);

\U2|Equal0~12505_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|Equal0~12505\ = \U2|Equal0~12487\ & \U2|Equal0~12502\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \U2|Equal0~12487\,
	datad => \U2|Equal0~12502\,
	combout => \U2|Equal0~12505\);

\U2|WideOr7~1377_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|WideOr7~1377\ = \U2|Equal0~12501\ # \U2|Equal0~12472\ & (\U2|Equal0~12504\ # \U2|Equal0~12505\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110011101100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \U2|Equal0~12504\,
	datab => \U2|Equal0~12501\,
	datac => \U2|Equal0~12472\,
	datad => \U2|Equal0~12505\,
	combout => \U2|WideOr7~1377\);

\U2|Equal0~12509_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|Equal0~12509\ = \U1|Q\(2) & \U1|Q\(5) & !\U1|Q\(4)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \U1|Q\(2),
	datac => \U1|Q\(5),
	datad => \U1|Q\(4),
	combout => \U2|Equal0~12509\);

\U2|Equal0~12511_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|Equal0~12511\ = \U1|Q\(3) & \U1|Q\(7) & \U1|Q\(2) & \U2|Equal0~12510\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \U1|Q\(3),
	datab => \U1|Q\(7),
	datac => \U1|Q\(2),
	datad => \U2|Equal0~12510\,
	combout => \U2|Equal0~12511\);

\U2|WideOr5~917_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|WideOr5~917\ = \U2|Equal0~12476\ & !\U2|Equal0~12511\ & (!\U2|Equal0~12512\ # !\U2|Equal0~12513\) # !\U2|Equal0~12476\ & (!\U2|Equal0~12512\ # !\U2|Equal0~12513\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001010100111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \U2|Equal0~12476\,
	datab => \U2|Equal0~12513\,
	datac => \U2|Equal0~12512\,
	datad => \U2|Equal0~12511\,
	combout => \U2|WideOr5~917\);

\U2|Equal0~12514_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|Equal0~12514\ = \U1|Q\(6) & \U1|Q\(3) & !\U1|Q\(1) & \U2|Equal0~12477\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \U1|Q\(6),
	datab => \U1|Q\(3),
	datac => \U1|Q\(1),
	datad => \U2|Equal0~12477\,
	combout => \U2|Equal0~12514\);

\U2|Equal0~12517_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|Equal0~12517\ = \U2|Equal0~12515\ & \U2|Equal0~12516\ & \U1|Q\(6) & \U1|Q\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \U2|Equal0~12515\,
	datab => \U2|Equal0~12516\,
	datac => \U1|Q\(6),
	datad => \U1|Q\(2),
	combout => \U2|Equal0~12517\);

\U2|WideOr5~918_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|WideOr5~918\ = \U2|WideOr2~584\ & \U2|WideOr5~917\ & !\U2|Equal0~12517\ & !\U2|Equal0~12514\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \U2|WideOr2~584\,
	datab => \U2|WideOr5~917\,
	datac => \U2|Equal0~12517\,
	datad => \U2|Equal0~12514\,
	combout => \U2|WideOr5~918\);

\U2|WideOr5~919_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|WideOr5~919\ = !\U2|Equal0~12487\ & !\U2|Equal0~12503\ # !\U2|Equal0~12677\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \U2|Equal0~12487\,
	datac => \U2|Equal0~12677\,
	datad => \U2|Equal0~12503\,
	combout => \U2|WideOr5~919\);

\U2|WideOr5~920_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|WideOr5~920\ = \U2|Equal0~12482\ & !\U2|Equal0~12519\ & (!\U2|Equal0~12677\ # !\U2|Equal0~12518\) # !\U2|Equal0~12482\ & (!\U2|Equal0~12677\ # !\U2|Equal0~12518\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000011101110111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \U2|Equal0~12482\,
	datab => \U2|Equal0~12519\,
	datac => \U2|Equal0~12518\,
	datad => \U2|Equal0~12677\,
	combout => \U2|WideOr5~920\);

\U2|WideOr5~921_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|WideOr5~921\ = !\U2|Equal0~12635\ & (!\U2|Equal0~12468\ # !\U2|Equal0~12479\) # !\U2|Equal0~12473\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001101111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \U2|Equal0~12479\,
	datab => \U2|Equal0~12473\,
	datac => \U2|Equal0~12468\,
	datad => \U2|Equal0~12635\,
	combout => \U2|WideOr5~921\);

\U2|WideOr5~922_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|WideOr5~922\ = \U2|WideOr5~918\ & \U2|WideOr5~921\ & \U2|WideOr5~919\ & \U2|WideOr5~920\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \U2|WideOr5~918\,
	datab => \U2|WideOr5~921\,
	datac => \U2|WideOr5~919\,
	datad => \U2|WideOr5~920\,
	combout => \U2|WideOr5~922\);

\U2|WideOr7~1381_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \U2|WideOr7~1381\ = !\U2|Equal0~12638\ & (!\U2|Equal0~12531\ # !\U2|Equal0~12511\)