📄 dds.map.rpt
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+---------------------------------------------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------+
; |DDS ; 471 (1) ; 36 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DDS ;
; |REG1:U1| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DDS|REG1:U1 ;
; |REG2:U3| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DDS|REG2:U3 ;
; |ROM:U2| ; 460 (460) ; 8 (8) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DDS|ROM:U2 ;
; |altsyncram:WideNor0_rtl_0| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DDS|ROM:U2|altsyncram:WideNor0_rtl_0 ;
; |altsyncram_uau:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DDS|ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated ;
; |SUM99:U0| ; 10 (10) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DDS|SUM99:U0 ;
+------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+---------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+---------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------+
; ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 1024 ; 1 ; -- ; -- ; 1024 ; DDS0.rtl.mif ;
+---------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------+
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; U2/OUTP[8] ; Stuck at GND due to stuck port data_in ;
; U3/Q[8] ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 2 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 36 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 10 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 10 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------------------------------------------+
; Source assignments for ROM:U2|altsyncram:WideNor0_rtl_0|altsyncram_uau:auto_generated ;
+---------------------------------+--------------------+------+-------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------+
+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: ROM:U2|altsyncram:WideNor0_rtl_0 ;
+------------------------------------+----------------------+-----------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+-----------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 1 ; Untyped ;
; WIDTHAD_A ; 10 ; Untyped ;
; NUMWORDS_A ; 1024 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; DDS0.rtl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CBXI_PARAMETER ; altsyncram_uau ; Untyped ;
+------------------------------------+----------------------+-----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Fri Dec 05 22:03:55 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds
Info: Found 10 design units, including 5 entities, in source file dds.vhd
Info: Found design unit 1: DDS-ART
Info: Found design unit 2: REG1-ART
Info: Found design unit 3: SUM99-ART
Info: Found design unit 4: REG2-ART
Info: Found design unit 5: ROM-ART
Info: Found entity 1: DDS
Info: Found entity 2: REG1
Info: Found entity 3: SUM99
Info: Found entity 4: REG2
Info: Found entity 5: ROM
Info: Elaborating entity "dds" for the top level hierarchy
Info: Elaborating entity "SUM99" for hierarchy "SUM99:U0"
Warning (10492): VHDL Process Statement warning at dds.vhd(90): signal "TEMP" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "REG1" for hierarchy "REG1:U1"
Info: Elaborating entity "ROM" for hierarchy "ROM:U2"
Info: Elaborating entity "REG2" for hierarchy "REG2:U3"
Warning: Reduced register "ROM:U2|OUTP[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "REG2:U3|Q[8]" with stuck data_in port to stuck value GND
Warning: Created node "ROM:U2|WideNor0~1" as a ROM by generating altsyncram megafunction to implement register logic with M512, M-LAB, M4K, or M9K memory block. Power-up state differs from the original design.
Info: Inferred 1 megafunctions from design logic
Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=1024, WIDTH_A=1) from the following design logic: "ROM:U2|WideNor0~1"
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborated megafunction instantiation "ROM:U2|altsyncram:WideNor0_rtl_0"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_uau.tdf
Info: Found entity 1: altsyncram_uau
Warning: Output pins are stuck at VCC or GND
Warning: Pin "Q[8]" stuck at GND
Info: Implemented 512 device resources after synthesis - the final resource count might be different
Info: Implemented 13 input pins
Info: Implemented 9 output pins
Info: Implemented 489 logic cells
Info: Implemented 1 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
Info: Allocated 143 megabytes of memory during processing
Info: Processing ended: Fri Dec 05 22:04:20 2008
Info: Elapsed time: 00:00:25
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