asynchronous_slavefifo_wr.v

usb-cy7c68013异步写传输代码verilog

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    16:28:16 07/11/15
// Design Name:    
// Module Name:   slavefifo_wr 
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 实现异步从属FIFO的写, 异部方式是通过IFCONFIG.3=1来设置的,IFCONFIG.3=0时为
// 同步方式
// 该模块是实现:系统上电复位后,直接由FPGA将数据写入
// FIFO的缓冲区,由PC机读取数据,验证slave fifo的写时序
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module Asynchronous_slavefifo_wr(clk, rst,FLAGB,FIFODATA, SLWR,SLCS,FIFOADR, led,flagb_led);


    input clk; //输入时钟50M
    input rst;
	//FLAGS,默认情况下是低电平有效
    input FLAGB; //EP6FF,EP6满标志
    inout [7:0] FIFODATA; 
    output SLWR,SLCS; //控制写入数据,异步模式下,在升沿将数据写入
	output [1:0] FIFOADR; //用于选择EP2,EP4,EP6和EP8中的哪一个FIFO与FD总线连接
    output led;
	 output flagb_led;
    // regs for output
	reg [1:0] FIFOADR;
	reg SLWR,SLCS;
	// regs for input
	reg flagb;
   
	// internal regs
	reg [7:0] ToFIFO;
	reg [3:0] CS,NS;
	reg [1:0] slwr_hcnt;
	reg [19:0] count;
	reg temp;
	reg led;
	reg clk1;
	assign flagb_led=FLAGB;
	always @(posedge clk)
	   clk1<=~clk1;
	parameter   SLWR_H = 2'b11;  //3个时钟周期,输入时钟为50M,SLWR高电平至少70ns
//
	parameter	IDLE			= 4'b0000,
				WADDR_SET		= 4'b0001,
				SLWR_LOW		= 4'b0010,
				DATA_WRITE		= 4'b0100,
				SLWR_HIGH		= 4'b1000;

	always @ (posedge clk1 or negedge rst)
	begin
		if(!rst)
			flagb<=0;
		else
			flagb<=FLAGB;
	end	
	/****sequential*******/
	always @ (posedge clk1 or negedge rst)
	begin
		if(~rst)
			CS<=IDLE;
		else 
			CS<=NS;
	end
    /******combination***/
	always @ (CS or flagb or  count or slwr_hcnt)
	begin
		case(CS)
			IDLE:
			begin
				if(flagb==1) //如果EP6非满则开始向FIFO写入数据
					NS=WADDR_SET;
				else
					NS=IDLE;
			end
			WADDR_SET: //设置FIFOADR
			begin
				NS=SLWR_LOW;
			end
			SLWR_LOW:
			begin
				NS=DATA_WRITE;
			end
			DATA_WRITE: //从将数据放置在总线上,写入FIFO
			begin
				NS=SLWR_HIGH;
			end
			SLWR_HIGH: //SLWR高电平持续四个时钟周期
			begin
				if(slwr_hcnt==SLWR_H)
				begin
					if(&count[19:0]) //for test
						NS=IDLE;
					else
					begin
						if(flagb==1)
							NS=SLWR_LOW;
						else
							NS=SLWR_HIGH;
					end
				end
				else
					NS=SLWR_HIGH;
			end
			default:
				NS=IDLE;
		endcase	
	end
	/*******state machine output******/
	always @ (posedge clk1 or negedge rst)
	begin
		if(~rst)
		begin
			ToFIFO<=8'b0;
			SLWR<=1;
                    SLCS<=1;
			FIFOADR[1:0]<=2'b00;
			slwr_hcnt<=0;
			temp<=0;
			count<=20'b0;
			led<=1;
		end
		else 
		begin
			case(NS)
				IDLE:
				begin
					ToFIFO<=8'b0;
					SLWR<=1;
                                  SLCS<=1;
					FIFOADR[1:0]<=2'b00;
					slwr_hcnt<=0;
					count<=0;
					temp<=0;
					led<=~led;
				end
				WADDR_SET: //设置EP6与总线相连
				begin
					FIFOADR[1:0]<=2'b10;
					slwr_hcnt<=0;
				end
				SLWR_LOW: 
				begin
					SLWR<=0;
                                  SLCS<=0;
					slwr_hcnt<=0;
					if(temp)
						count<=count+1;
					else
					begin
						temp<=1;
						count<=0;
					end
				end
				DATA_WRITE:   //从SRAM读取数据放置在总线上,等待SLWR
                                         //的上升沿到来,将数据写入FIFO
				begin
					ToFIFO[7:0]<=count[7:0]; 
				end
				SLWR_HIGH: //SLWR高电平要持续四个时钟周期
				begin
					SLWR<=1;
                                  SLCS<=1;
					slwr_hcnt<=slwr_hcnt+1;	
				end
				default:
				begin
					ToFIFO<=8'b0;
					SLWR<=1;
                                  SLCS<=1;
					FIFOADR[1:0]<=2'b00;
					slwr_hcnt<=0;
					temp<=0;
					count<=0;
				end
			endcase	
		end
	end	

	assign FIFODATA[7:0]=flagb?ToFIFO[7:0]:8'bz;

endmodule