multi8x8.fit.qmsg

VHDL实现的8位乘法器

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.114 ns register register " "Info: Estimated most critical path is register to register delay of 0.114 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SREG8B:inst1\|reg8\[7\] 1 REG LAB_X26_Y3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X26_Y3; Fanout = 1; REG Node = 'SREG8B:inst1\|reg8\[7\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "" { SREG8B:inst1|reg8[7] } "NODE_NAME" } "" } } { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.114 ns) 0.114 ns SREG8B:inst1\|reg8\[6\] 2 REG LAB_X26_Y3 1 " "Info: 2: + IC(0.000 ns) + CELL(0.114 ns) = 0.114 ns; Loc. = LAB_X26_Y3; Fanout = 1; REG Node = 'SREG8B:inst1\|reg8\[6\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "0.114 ns" { SREG8B:inst1|reg8[7] SREG8B:inst1|reg8[6] } "NODE_NAME" } "" } } { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.114 ns ( 100.00 % ) " "Info: Total cell delay = 0.114 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "0.114 ns" { SREG8B:inst1|reg8[7] SREG8B:inst1|reg8[6] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 29 12:10:08 2008 " "Info: Processing ended: Sat Mar 29 12:10:08 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}